Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With stress relief
Reexamination Certificate
1997-11-26
2001-03-27
Whitehead, Jr., Carl (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
With stress relief
C257S672000, C257S676000, C257S678000, C257S723000, C257S777000
Reexamination Certificate
active
06208018
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an apparatus and a method for upgrading or remediating semiconductor devices. In particular, the present invention relates to utilizing a remediation, modification or upgrade chip or other component in a piggyback configuration with an existing bare-chip assembly to achieve an upgrade, modify chip operating parameters or remedy a design or fabrication problem.
2. State of the Art
Definitions: The following terms and acronyms will be used throughout the application and are defined as follows:
BGA—Ball Grid Array: An array of minute solder balls disposed on an attachment surface of a semiconductor die wherein the solder balls are refluxed for simultaneous attachment and electrical communication of the semiconductor die to a printed circuit board.
COB—Chip On Board: The techniques used to attach semiconductor dice to a printed circuit board or similar carrier substrate, including flip chip attachment, wirebonding, and tape automated bonding (“TAB”). COB also references the resulting end product.
Flip Chip: A chip or die that has a pattern or array of terminations spaced around the active surface of the die for face down mounting of the die to a substrate.
Flip Chip Attachment: A method of attaching a semiconductor die to a substrate in which the die is inverted so that the connecting conductor pads on the face of the device are set on mirror-image pads on the substrate (such as a printed circuit board) and generally bonded by solder reflux or a conductive-polymer curing.
Glob Top: A glob of encapsulant material (usually epoxy or silicone or a combination thereof) surrounding a semiconductor die in a COB assembly.
PGA—Pin Grid Array: An array of small pins extending substantially perpendicularly from the major plane of a semiconductor die, wherein the pins conform to a specific arrangement on a printed circuit board or other substrate for attachment thereto.
SLCCC—Slightly Larger than Integrated Circuit Carrier: An array of minute solder balls disposed on an attachment surface of a semiconductor die similar to a BGA, but having a smaller solder ball pitch and diameter than a BGA.
TAB—Tape Automated Bonding: A conductor-placement structure wherein conductive traces pre-formed on a dielectric film or flexible sheet, such as a polyimide, are used to electrically connect bond pads of a semiconductor die to conductors of a carrier such as a leadframe or printed circuit board.
State-of-the-art COB technology generally consists of three semiconductor die-to-printed circuit board conductive attachment techniques: flip chip attachment, wirebonding, and TAB.
Flip chip COB attachment consists of attaching a semiconductor die, generally having a BGA, a SLICC or PGA, to a printed circuit board. With the BGA or SLICC, the solder or other conductive ball arrangement on the semiconductor die must be a mirror-image of the connecting bond pads on the printed circuit board such that precise connection is made. The semiconductor die is bonded to the printed circuit board by refluxing the solder balls. With the PGA, the pin arrangement of the semiconductor die must be a mirror-image of the pin recesses on the printed circuit board. After insertion, the semiconductor die is generally bonded by soldering the pins into place. In all of the foregoing techniques, insulative under-fill encapsulant is generally disposed between the semiconductor die and the printed circuit board for environmental protection and to enhance the attachment of the die to the board.
Wirebonding and TAB attachment to produce a COB generally begin with attaching a semiconductor die to the surface of a printed circuit board with an appropriate adhesive, such as an epoxy. In wirebonding, a plurality of bond wires is extended and attached, one at a time, between each bond pad on the semiconductor die and a corresponding lead or trace end on the printed circuit board. The bond wires are generally attached through one of three industry-standard wirebonding techniques: ultrasonic bonding—using a combination of pressure and ultrasonic vibration bursts to form a metallurgical cold weld; thermocompression bonding—using a combination of pressure and elevated temperature to form a weld; and thermosonic bonding—using a combination of pressure, elevated temperature, and ultrasonic vibration bursts. With TAB, ends of metal traces carried on an insulating tape or film such as a polyimide are respectively gang-bonded using thermocompression techniques to the bond pads on the semiconductor die and to the lead or trace ends on the printed circuit board. An encapsulant is generally subsequently applied over the die and attendant the bond wires to prevent contamination or any physical damage to the assembly.
During a production run of an integrated circuit, a design parameter may change or a design or fabrication may be detected in one or more circuits of a semiconductor chip. When such occur, the semiconductor chips of that production run may have to be scrapped if not exhibiting at least minimum performance characteristics. Although it may be possible to remediate the semiconductor chips with the addition of an adjacent chip or other circuit on the board, increased miniaturization of components and the boards to which they are mounted, as well as greater packaging density of integrated circuit assemblies, reduces or eliminates the potential space or “real estate” on the board upon which to locate remediation or upgrade circuitry or chips. Further, in many instances, it would be desirable to employ semiconductor dice in circuits for which they were not initially designed or intended, such as employing a die having a lower voltage requirement in a circuit providing a higher voltage power input. Such adaptability of dice to various operating environments may be significant, and even critical, during cycles in the industry wherein certain components are in short supply and others might be substituted if a viable technique for doing so existed.
U.S. Pat. No. 5,012,323 issued Apr. 30, 1991, to Farnworth teaches combining a pair of dice mounted on opposing sides of a leadframe. An upper, smaller die is back-bonded to the upper surface of the leads of the leadframe via a first adhesively coated, insulated film layer. A lower, larger die is face-bonded to the lower lead frame die-bonding region via a second, adhesively coated, insulative film layer. The wire-bonding pads on both the upper die and lower die are interconnected with the ends of their associated lead extensions with gold or aluminum bond wires. The lower die must be slightly larger than the upper die in order that the die pads are accessible from above through a bonding window in the leadframe such that gold wire connections can be made to the lead extensions.
U.S. Pat. No. 5,128,831 issued Jul. 7, 1992, to Fox et al. teaches vertically-stacked die, each in a sub-module, the sub-modules connected by solder-filled vias and the assembly connected to a board through a PGA.
U.S. Pat. No. 5,291,061 issued Mar. 1, 1994, to Ball teaches a multiple stacked die device containing up to four stacked dice supported on a die-attach paddle of a leadframe, the assembly not exceeding the height of then-current single die packages, and wherein the bond pads of each die are wirebonded to lead fingers. The low profile of the device is achieved by close-tolerance stacking which is made possible by a low-loop-profile wirebonding operation and thin adhesive layers between the stacked dice.
U.S. Pat. No. 5,323,060 issued Jun. 21, 1994, to Fogal et al. teaches a multichip module that contains stacked dice devices, the terminals or bond pads of which are wirebonded to a substrate or to adjacent dice devices.
U.S. Pat. No. 5,422,435 to Takiar et al. teaches dice stacked to form a multi-chip module (MCM) and having wire bonds extending to each other and to the leads of a conductor-bearing carrier member such as a leadframe.
U.S. Pat. No. 5,434,735 issued Jul. 18, 1995, to Shokrgozar et al. teaches a structure similar to that of Fox et
Bruce Jeffrey D.
Ma Manny Kin F.
Jr. Carl Whitehead
Micro)n Technology, Inc.
Trask & Britt
Warren Matthew E.
LandOfFree
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