Photoresist scum for copper dual damascene process

Details Photoresist scum for copper dual damascene process Photoresist scum for copper dual damascene process

2002-01-10

2004-10-05

Chen, Kin-Chan (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S723000, C438S725000

Reexamination Certificate

active

06800558

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method for improved removal of photoresist remnants or scum as this scum occurs as part of trench lithography applied for dual damascene processes.
(2) Description of the Prior Art
The creation of semiconductor devices comprises the creation of multiple conductive regions, isolated from each other by dielectric layers, on the surface of a semiconductor substrate. Some of the dielectrics, such as silicon dioxide, can be grown on the surface of the substrate or can be physically deposited by for instance a sputtering process or by other chemical methods of dielectric deposition. The native properties of a dielectric can further be altered by doping the dielectric layer by either n-type dopants such as arsenic and phosphorous or p-type dopants such as indium or boron.
To interconnect the various layers of conductive lines that are created within the structure of a semiconductor device, contact and via openings are created in the dielectric. These openings are filled with a conductive material that can contain tungsten, titanium nitride, molybdenum, silicide and polysilicon but typically contains tungsten, wolfram or copper.
The process of creating one or more openings starts with the deposition of a layer of dielectric (the dielectric into which the openings are to be made) over which a layer of photoresist is deposited. The layer of photoresist is patterned in accordance with the desired pattern of the openings, the photoresist is removed above the layer of dielectric in accordance with the pattern for the to be created openings. The dielectric layer is then etched, that is the dielectric is removed in accordance with the pattern of the openings. A dry etch is typically performed, exposing the dielectric layer to a plasma that is created by using one or more gasses that expose the surface of the dielectric where the photoresist has been removed. The type of etchant that is applied for a particular step of etching the openings will be determined by the processing and functional application of the openings within the overall device structure.
Increased circuit density brings with it the need to create openings that have a high aspect ratio. For high aspect ratio openings, it is critical that openings are created that have a profile that allows for complete penetration of the conductive material such as metal that fills the opening while the profile of the opening must be such that good adhesion is established between the deposited metal and the sidewalls of the openings. To avoid distortion of the photoresist patterns that are used to create the openings on the dielectric layer, Anti Reflective Coating (ARC) is frequently applied over the surface of the opening. Photolithographic patterning problems can be caused by the increase in use of highly reflective materials such as polysilicon, aluminum, and metal silicides in the creation of the semiconductor device. These materials can cause unwanted reflections from the underlying layers, resulting in distortion of the creation of the openings. Anti Reflective Coatings (ARC) are used to minimize the adverse impact due to reflectance from these reflective materials.
The invention addresses the concern that for trench photolithography, as this technology is currently applied for the creation of dual damascene structures, no pre-treatment method of the applied layer of photoresist is available for the complete removal of photoresist scum after the layer of photoresist has been developed. The remaining photoresist scum distorts the etch profile, causing poor etch results and the formation of poorly defined interconnect structures such as dual damascene structures. The invention provides such a method that removes photoresist scum and that therefore can be applied for the creation of well defined conductive interconnects.
U.S. Pat. No. 6,025,259 (Yu et al.) shows a photoresist scum in dual damascene process.
U.S. Pat. No. 5,547,642 (Seiwa et al.) shows a photoresist scum removal process.
U.S. Pat. No. 61228,755 (Kusumi et al.) shows a dual damascene process.
U.S. Pat. No. 6,074,941 (Hsieh et al.) shows a poison via and plasma treatment process.
U.S. Pat. No. 5,643,407 (Chang) shows a shows a poison via and bake treatment process.
SUMMARY OF THE INVENTION
A principle objective of the invention is to remove photoresist scum from openings that have been created using a layer of photoresist.
In accordance with the objective of the invention a new method is provided of treating the wafer in or on the surface of which a patterned and developed layer of photoresist has been created for the purpose of creating openings in underlying layers of semiconductor material. The wafer is exposed, after the via or plug etch has been completed, to high temperature of between about 250 and 400 degrees C., using a hot plate or a furnace, in an environment of low or atmospheric pressure. The exposure of the wafer to elevated temperatures can be in an environment with or without inert gasses or with or without the presence of a base or forming gas. The dual damascene structure is then completed using a layer of DUV photo, an trench opening is created in the layer of DUV photoresist that aligns with the via opening.


REFERENCES:
patent: 5547642 (1996-08-01), Seiwa et al.
patent: 5643407 (1997-07-01), Chang
patent: 6017817 (2000-01-01), Chung et al.
patent: 6025259 (2000-02-01), Yu et al.
patent: 6042999 (2000-03-01), Lin et al.
patent: 6074941 (2000-06-01), Hsieh et al.
patent: 6228755 (2001-05-01), Kusumi et al.
patent: 6251774 (2001-06-01), Harada et al.
patent: 6284657 (2001-09-01), Chooi et al.
patent: 6319809 (2001-11-01), Chang et al.

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