Phase-locked loop synthesizer

Details Phase-locked loop synthesizer Phase-locked loop synthesizer

1994-09-22

1996-04-23

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

331 1A, 331 25, H03D 324

Patent

active

055111017

ABSTRACT:
To provide stable oscillation frequencies at small step intervals even with a high reference frequency, a PLL circuit of the present invention includes variable frequency oscillation means for outputting an oscillation frequency signal, pulse train generating means receiving the oscillation frequency signal as a clock signal, for converting a train of n clocks to m pulses where n and m are positive integers, generating sequential pulses produced by arranging part of the m pulses so that they have non-uniform numbers of clocks, and outputting m periodical, sequential pulse trains so that the pulses having the non-uniform numbers of clocks are arranged differently, phase comparing means for outputting a phase error signal by determining a phase error between the reference frequency signal and the oscillation frequency signal based on the reference frequency signal and the m sequential pulse trains, and filtering means for filtering the phase error signal to produce a frequency control signal, and supplying the frequency control signal to the variable frequency oscillation means.

REFERENCES:
patent: 3731219 (1973-05-01), Mader et al.
patent: 5068628 (1991-11-01), Goshal

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