Phase-locked loop (PLL) circuit for selectively correcting...

Details Phase-locked loop (PLL) circuit for selectively correcting... Phase-locked loop (PLL) circuit for selectively correcting...

2007-06-05

2007-06-05

Tran, Khai (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C327S147000

Reexamination Certificate

active

10379776

ABSTRACT:
A phase-locked loop (PLL) circuit includes multiple selectable feedback paths and a mode selector for selecting different feedback paths in different operating modes. The PLL circuit may correct for clock skew or produce a desired degree of clock skew between input and output clock signals in different operating modes.

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patent: 2001/0055357 (2001-12-01), Chen

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