4. Multiplex communications
  5. Pathfinding or routing
  6. Switching a message which includes an address header

Raul Oteyza

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Phase-locked loop (PLL) circuit for selectively correcting...

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate

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Phase-locked loop (PLL) circuit for selectively correcting...

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate

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Queuing fibre channel receive frames

Electrical computers and digital processing systems: memory – Address formation – Combining two or more values to create address
Reexamination Certificate

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Variable access fairness in a fibre channel arbitrated loop

Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate

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Profile ID: LFUS-PAI-P-2557267

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