Phase-locked loop (PLL) circuit for selectively correcting...

Details Phase-locked loop (PLL) circuit for selectively correcting... Phase-locked loop (PLL) circuit for selectively correcting...

2002-06-03

2003-11-11

Tran, Khai (Department: 2631)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S373000

Reexamination Certificate

active

06647081

ABSTRACT:

BACKGROUND
Phase Locked Loop (PLL) circuits may be used for frequency control. PLL circuits may be configured as frequency multipliers, demodulators, tracking generators or clock recovery circuits. A PLL circuit operates by producing an oscillator frequency to match the frequency of an input signal. In the locked condition, any slight change in the input signal first appears as a change in phase between the input signal and the oscillator frequency. This phase shift acts as an error signal to change the frequency of the local PLL oscillator to match the change in the input signal.
A clock signal transmitted from a clock generation circuit to another, downstream clock generation circuit may incur delays as it passes through circuit components in its path. These delays may produce an offset, or skew, between the signals output from the two clock generation circuits. A PLL circuit may be used to reduce this skew.
SUMMARY
A phase-locked loop (PLL) circuit including multiple selectable feedback paths may be used to correct for clock skew between an external clock signal and an internal clock signal in an operating mode. The clock skew may be caused, at least in part, by a delay-inducing element in the clock signal path. In this operating mode, a mode selector may select a feedback path including the clock tree so that the PLL circuit corrects for the delay caused by the clock tree.
The mode selector may select another feedback path in another operating mode in which a certain amount of skew is desirable for that mode's clocking scheme. The selected feedback path may include additional delay—inducing elements such as string of buffers which introduce additional delay into the PLL feedback path. The additional delay may cause the PLL circuit to overcorrect for the skew introduced by the clock tree, thereby producing the desired clock skew between the external and internal clock signals.


REFERENCES:
patent: 6014048 (2000-01-01), Talaga et al.

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