Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
2005-10-11
2005-10-11
Fan, Chieh M. (Department: 2634)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C375S371000, C375S354000
Reexamination Certificate
active
06954510
ABSTRACT:
There is provided a phase-locked loop lock detector circuit for detecting a lock or unlock state of a PLL circuit. A synchronization circuit synchronizes a lock window signal with a reference frequency signal. A rising edge detection circuit and a falling edge detection circuit output a state of an error signal at a rising edge of an output signal of the synchronization circuit and at a rising edge of an inverted lock window signal, respectively. A logic circuit performs an AND operation on outputs of the detection circuits, and outputs a signal indicating the lock or unlock state.
REFERENCES:
patent: 4959617 (1990-09-01), Martin
patent: 5126602 (1992-06-01), Lee et al.
patent: 5455540 (1995-10-01), Williams
patent: 5640523 (1997-06-01), Williams
patent: 5834950 (1998-11-01), Co et al.
patent: 5923190 (1999-07-01), Yamaguchi
patent: 6081572 (2000-06-01), Filip
patent: 6114889 (2000-09-01), Lee
F. Chau & Associates LLC
Fan Chieh M.
Perilla Jason M.
Samsung Electronics Co,. Ltd.
LandOfFree
Phase-locked loop lock detector circuit and method of lock... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Phase-locked loop lock detector circuit and method of lock..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Phase-locked loop lock detector circuit and method of lock... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3469604