Phase-locked loop lock detector circuit and method of lock...

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

Reexamination Certificate

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C375S371000, C375S354000

Reexamination Certificate

active

06954510

ABSTRACT:
There is provided a phase-locked loop lock detector circuit for detecting a lock or unlock state of a PLL circuit. A synchronization circuit synchronizes a lock window signal with a reference frequency signal. A rising edge detection circuit and a falling edge detection circuit output a state of an error signal at a rising edge of an output signal of the synchronization circuit and at a rising edge of an inverted lock window signal, respectively. A logic circuit performs an AND operation on outputs of the detection circuits, and outputs a signal indicating the lock or unlock state.

REFERENCES:
patent: 4959617 (1990-09-01), Martin
patent: 5126602 (1992-06-01), Lee et al.
patent: 5455540 (1995-10-01), Williams
patent: 5640523 (1997-06-01), Williams
patent: 5834950 (1998-11-01), Co et al.
patent: 5923190 (1999-07-01), Yamaguchi
patent: 6081572 (2000-06-01), Filip
patent: 6114889 (2000-09-01), Lee

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