Phase locked loop including control circuit for reducing...

Details Phase locked loop including control circuit for reducing... Phase locked loop including control circuit for reducing...

2005-11-01

2005-11-01

Fan, Chieh M. (Department: 2634)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S371000

Reexamination Certificate

active

06961399

ABSTRACT:
A PLL circuit includes a control circuit for generating a reference control signal. A reception divider, reference divider, and transmission divider respectively divide an output signal of a receiver VCO according to a reception division data signal, an output signal of a crystal oscillator according to a reference division data signal, and an output signal of a transmitter VCO according to a transmission division data signal. A first and second phase detector respectively detect frequency and phase differences between a reception divider output and a reference divider output and between a transmission divider output and the reference divider output.

REFERENCES:
patent: 5008629 (1991-04-01), Ohba et al.
patent: 5128623 (1992-07-01), Gilmore
patent: 5748043 (1998-05-01), Koslov
patent: 5838205 (1998-11-01), Ferraiolo et al.
patent: 0435552 (1991-03-01), None

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