Phase locked loop for improving a phase locking time

Details Phase locked loop for improving a phase locking time Phase locked loop for improving a phase locking time

1997-04-01

1999-07-20

Le, Amanda

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

331 25, H04L 700

Patent

active

059265159

ABSTRACT:
A PLL for improving a locking time in a radio communication system, includes: a storage unit for digitally storing a series of different control voltages; a digital/analog converter for converting a read control voltage into an analog control voltage; a voltage controlled oscillator oscillating at a frequency in accordance with a level of a supplied analog control voltage or signal; a variable divider for frequency dividing the voltage controlled oscillator output in accordance with a variable dividing ratio determined by a system operating mode; a phase comparator for comparing a phase of the variable divider output with an externally supplied reference signal, and for outputting a phase difference signal indicative of a comparison result; a low-pass filter low-pass for filtering the phase difference signal; a level detector for comparing a level of the low-pass filter output with a reference level, and for generating a digital comparison result signal; a controller for reading one of the series of stored control voltages using the level detector output supplied to the digital/analog converter, and for performing a read operation until the level detector output is within a predetermined range; and a switch for supplying the digital/analog converter output to the voltage controlled oscillator.

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