Phase locked distributed time reference for digital processing a

Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses

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713503, 713600, G06F 104, G06F 112

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active

060237686

ABSTRACT:
A phase locked distributed time reference system for use in multiplexed communication bus structures. This system is composed of two parts, a master and a slave time reference or clock. The master time reference is a high accuracy clock that is a dedicated distributed clock system which uses an appropriate communication bus, such as the MIL-STD-1553, for distribution but which completely bypasses the other bus protocols and operations. This master time reference would ideally be placed on the processor bus for immediate access. The high order segment, which extend the master time reference to the desired range, i.e. 30 days or longer, is transmitted via the normal bus communications without the need for any special data handling. The only requirement is to update the signal at a cyclic rate faster than the roll over time of the low order segment plus any delay in transmission and assembly of the two halves. The two bits of the low order segment of the slave time reference are frequency multiplexed and are not transmitted via the normal bus communications. The operation of the present invention uses only two of the low order bits to establish a reference. These two bits are reconstructed in the slave time reference by a decoder, a phase locked loop frequency multiplier, and a counter. The two bits are used to compare to a regenerated time from the counter to determine the loss of synchronization and to resynchronize the counter.

REFERENCES:
patent: 4860285 (1989-08-01), Miller et al.
patent: 5367641 (1994-11-01), Pressprich et al.
patent: 5457718 (1995-10-01), Anderson et al.
patent: 5504878 (1996-04-01), Coscarella et al.
patent: 5920600 (1999-07-01), Yamaoka et al.

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