Phase compensating circuit

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

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Details

375368, 3701053, 348537, H04M 1500, H04N 500

Patent

active

054208955

ABSTRACT:
A phase compensating circuit in a video signal processing system utilizing a frequency folding technique which requires the recovery of an exact sampling phase is disclosed. A predetermined pattern is inserted during an encoding operation, and the frequency of the inserted pattern is discriminated during a decoding. During this process, when a comparison is made as to whether the original phase lies at the front or at the rear of the received phase, the comparison is not made with an exact value, but with a predetermined range of values by taking into account the inherent variability in delay values, for example, due to temperature variations, of delaying devices of a clock adjusting part. In this regard, the sum total of the delays of the delaying devices is made to include one clock period by taking into account the temperature characteristics of the delaying devices, with the result that clocks having a relatively exact phase can be generated based on the pattern inserted during an encoding.

REFERENCES:
patent: 4414676 (1983-11-01), Kraul et al.
patent: 4819251 (1989-04-01), Nelson
patent: 4876699 (1989-10-01), Nelson
patent: 5018140 (1991-05-01), Lee et al.
patent: 5134637 (1992-07-01), Beyer et al.

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