Phase change memory erasable and programmable by a row decoder

Details Phase change memory erasable and programmable by a row decoder Phase change memory erasable and programmable by a row decoder

2011-01-11

2011-01-11

Elms, Richard (Department: 2824)

Static information storage and retrieval

Systems using particular element

Amorphous

C365S148000, C977S754000

Reexamination Certificate

active

07869268

ABSTRACT:
An integrated circuit includes a non-volatile memory having memory cells each having a memory point and a selection transistor having a control terminal connected to a word line, a row decoder for supplying word line selection signals, and at least one generator for supplying memory cells with an erase or programming voltage or current. Word line drivers are interposed between the row decoder and the word lines, and are arranged for applying to a word line selected by the row decoder control pulses, the profile of which corresponds to a profile of an erase or programming voltage or current pulse. Application is for particularly but not exclusively to phase change memories.

REFERENCES:
patent: 4272833 (1981-06-01), Taylor
patent: 6862213 (2005-03-01), Hamaguchi
patent: 6995999 (2006-02-01), Morimoto
patent: 7050328 (2006-05-01), Khouri et al.
patent: 2005/0117397 (2005-06-01), Morimoto
patent: 2005/0169093 (2005-08-01), Choi et al.
patent: 2005/0237820 (2005-10-01), Takemura et al.

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