Phase adjusted delay loop executed by determining a number...

Details Phase adjusted delay loop executed by determining a number... Phase adjusted delay loop executed by determining a number...

2007-12-18

2007-12-18

Cao, Chun (Department: 2115)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

Using delay

C712S219000

Reexamination Certificate

active

10920835

ABSTRACT:
In an embodiment of the invention, a method for a phase adjusted delay loop, includes: determining a requested delay value for a code path; and executing a delay loop in the code path in order to obtain a loop delay value that is in phase with the requested delay value. The act of executing the delay loop may include: executing at least one No-operation instruction (NOP) to adjust the loop delay value and to adjust the phase of the loop delay value.

REFERENCES:
patent: 5958044 (1999-09-01), Brown et al.
patent: 6275929 (2001-08-01), Blum et al.

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