Phase adjust using relative error

Details Phase adjust using relative error Phase adjust using relative error

2008-01-29

2008-01-29

Ton, David (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error count or rate

C327S009000

Reexamination Certificate

active

11123355

ABSTRACT:
A system may adjust the times at which data is sampled by separate sampling mechanisms. Here, it may be desirable to ensure that one sampler samples data at substantially the same time as the other sampler. For example, output data from a high speed sampler that samples received data may be compared with an output of an analog to digital converter that samples the received data at a lower data rate. This difference or relative error may be accumulated over a period of time for given values of delay applied to the clock for the analog to digital converter. In this way, a delay value that minimizes the relative error may be selected as a desired delay value.

REFERENCES:
patent: 4873491 (1989-10-01), Wilkins
patent: 5294926 (1994-03-01), Corcoran
patent: 6711226 (2004-03-01), Williams et al.
patent: 7148828 (2006-12-01), Fernandez et al.
patent: 7202707 (2007-04-01), Momtaz

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