Personalized area leadframe coining or half etching for reduced

Details Personalized area leadframe coining or half etching for reduced Personalized area leadframe coining or half etching for reduced

1994-11-04

1996-08-13

Saadat, Mahshid

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

With stress relief

257674, 257692, 361807, 361813, H01L 23495, H01L 2348

Patent

active

055459218

ABSTRACT:
A lead on chip (LOC) semiconductor leadframe package provides notched lead-fingers to eliminate mechanical shear-stress at the peripheral edge of a semiconductor chip. Opposite rows of substantially flat cantilevered lead-fingers are attached by double-sided adhesive tape in thermal contact with the active face of a chip. The lead-fingers are routed in personalized paths over the face of the chip to cover a large surface area to aid heat dissipation. All wirebond connections between the lead-fingers and the chip are made at a centerline connection strip running down the center of the chip. Each of the cantilevered lead-fingers has a notched portion positioned directly over the vulnerable peripheral chip edge to reduce thermal, mechanical shear-stress. Additionally, since corrosion typically follows a lead path, the notch provides an increasing path length to prevent corrosive ingress over the chip face.

REFERENCES:
patent: 4209355 (1980-06-01), Burns
patent: 4210926 (1980-07-01), Hacke
patent: 4722060 (1988-01-01), Qunin et al.
patent: 4754912 (1988-07-01), Burns
patent: 4797726 (1989-01-01), Manabe
patent: 4803540 (1989-02-01), Moyer et al.
patent: 4862245 (1989-08-01), Pashby et al.
patent: 4924292 (1990-05-01), Kaufman
patent: 5068712 (1991-11-01), Murakami et al.

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