Peripheral circuits including high voltage transistors with LDD

Details Peripheral circuits including high voltage transistors with LDD Peripheral circuits including high voltage transistors with LDD

1997-02-21

1999-06-29

Meier, Stephen D.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257347, H01L 2976, H01L 2994, H01L 31062, H01L 31113

Patent

active

059172185

ABSTRACT:
A peripheral circuit for a nonvolatile integrated circuit memory device includes a semiconductor substrate with a well region having a first conductivity type adjacent a face of the substrate. A first transistor on the well region includes a first gate insulating layer, a first gate electrode, first lightly doped regions in the well region adjacent opposite sides of the first gate electrode, and first heavily doped regions in the well region adjacent the first lightly doped regions opposite the first gate electrode. The first gate insulating layer is adjacent the first well region and has a first thickness. The first gate electrode is on the first gate insulating layer, and the first lightly doped regions define a first transistor channel therebetween and have a second conductivity type and a first light dopant concentration. The first heavily doped regions have the second conductivity and a first heavy dopant concentration. A second transistor on the well region includes a second gate insulating layer, a second gate electrode, second lightly doped regions in the second well region adjacent opposite sides of the second gate electrode, and second heavily doped regions in the second well region adjacent the second lightly doped regions opposite the second gate electrode. The second gate insulating layer has a second thickness less than the first thickness. The second lightly doped regions define a second transistor channel therebetween and have the second conductivity type and a second light dopant concentration. The second heavily doped regions have the first conductivity and a second heavy dopant concentration. Related methods are also discussed.

REFERENCES:
patent: 5182619 (1993-01-01), Pfiester
patent: 5329138 (1994-07-01), Mitani et al.
patent: 5355011 (1994-10-01), Takata

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