Semiconductor device manufacturing: process – Radiation or energy treatment modifying properties of...
Reexamination Certificate
2002-03-12
2004-05-11
Kielin, Erik J. (Department: 2813)
Semiconductor device manufacturing: process
Radiation or energy treatment modifying properties of...
C438S439000, C361S234000
Reexamination Certificate
active
06734117
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to semiconductor processing and securing a wafer to a chuck during lithographic processing.
In semiconductor processing, lithographic systems transfer a pattern from a mask to a resist coated wafer by illuminating the mask with a source of radiation and projecting the resulting patterned radiation onto the resist coated wafer. In an optical system the energy source is light and in an electron beam system the energy source is a beam of electrons. To place the pattern in the right location on the wafer, the wafer must be properly positioned relative to the mask. Traditionally this is accomplished by clamping the wafer to a chuck mounted on a movable wafer stage and aligning the mask and wafer using an alignment system which measures alignment marks on the two substrates and then moves one of them, typically the wafer, until the alignment marks have the correct relative locations. In other lithography systems a mask is not used; instead a small shaped beam of radiation is used to sequentially pattern the wafer.
In conventional lithography systems, the alignment procedure is carried out once prior to starting the lithographic process. Lithographic systems use this initial alignment throughout the lithographic process under the assumption that no phenomena during the lithographic process could cause a significant misalignment impacting the yield. This saves time and increases throughput as subsequent realignments would reduce the time available for exposing wafers.
The energy projected into the wafer also heats it. The amount of heat introduced may grow in the future as new lithography technologies are introduced and as larger wafers come into use. One example of a new lithography technology that may increase wafer heating is electron beam projection lithography. In electron beam projection lithography only a fraction of the electron energy is absorbed by the resist and the rest of the energy is absorbed in the wafer. Because these semiconductor wafers have positive thermal expansion coefficients, the wafers will try to expand as the energy is absorbed. Wafers are typically attached to a wafer chuck to constrain or limit this expansion. Accordingly, the wafer's dimensions and location will change little if the chuck's dimensions do not change during the exposure. This assumes, however, that either the chuck's thermal expansion coefficient is small, or heat from the wafer is conducted efficiently out of the chuck by means of a heat transfer system. It further assumes that the wafer or parts of the wafer do not slip on the chuck.
However, slippage will occur if the thermal stresses building up in the heated wafer overcome the forces holding the wafer in place on the chuck. If parts of the wafer that have not yet been exposed slip on the chuck, these parts will no longer be aligned properly with respect to the mask or the lithography tool, and misalignment will occur, leading in general to reduced process yield.
In some cases, increasing the clamping strength of the wafer to the chuck can overcome the slippage and misalignment problems associated with the increased thermal stress. For example, vacuum chucks used in conventional optical lithography appear to clamp a wafer well-enough to avoid slippage and misalignment caused by thermal stress. Unfortunately, this solution may not continue to work as the wafer size increases and optical lithography techniques heat the wafers to higher temperatures. Eventually, the increased thermal stress caused during even optical lithography may overcome the vacuum chuck's ability to clamp the wafer.
In the case of charged particle or electron beam projection lithography (EBPL) and extreme ultraviolet lithography (EUV), clamping the wafer securely to the chuck is even more of a problem. Because EBPL and EUV expose the wafer in a vacuum or near vacuum, the preferred chuck is an electrostatic chuck. These chucks typically do not achieve as high a holding force as vacuum chucks and thermal stress accompanied by misalignment is a much more serious issue. During the exposure, the wafer heats up in exposed regions creating thermal stress. If the thermal stresses exceed the local clamping force of the chuck, portions of the wafer break away from the chuck momentarily and slip along the surface of the chuck before reattaching. The subsequent lithographic patterns will be misaligned if the thermal stress and slipping extend to the unexposed regions of the wafer.
SUMMARY OF THE INVENTION
In one aspect of the invention, a method of reducing the movement of a semiconductor wafer during fabrication includes operating to selectively clamp and unclamp the wafer to the multiple segments of a segmented chuck, exposing a region of the wafer clamped to a segment of the chuck to an energy source during the fabrication process that causes thermal stresses in the exposed segment, unclamping the exposed region of the wafer from the corresponding segment of the chuck to relieve the thermal stresses, and reclamping the exposed region of the semiconductor wafer to the segmented chuck as the thermal stresses are relieved.
In yet another aspect of the invention, a method of reducing the movement of a semiconductor wafer fabricated using a charged particle energy source includes clamping the wafer to the multiple segments of a segmented electrostatic chuck wherein each region of the semiconductor wafer overlying a segment of the chuck includes at least one die or chip site, and operating the segmented chuck to selectively clamp and unclamp one or more individual regions of the wafer, exposing a region of the wafer clamped to a segment of the chuck to a charged particle energy source during the charged particle fabrication process causing thermal stress in the clamped segment, unclamping the exposed region of the wafer from the corresponding segment of the chuck to relieve the thermal stresses, and reclamping the exposed region of the wafer to the segmented chuck after the thermal stresses of the exposed region are relieved.
The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features and advantages of the invention will become apparent from the description, the drawings, and the claims.
REFERENCES:
patent: 4733091 (1988-03-01), Robinson et al.
patent: 5822172 (1998-10-01), White
patent: 6141203 (2000-10-01), Sherman
M. Nakasuji et al., “Low voltage and high speed operating electrostatic wafer chuck using sputtered tantalum oxide membrane, ” Journal of Vacuum Science and Technology vol. A12(5), pp. 2834-2839(1994).
Kielin Erik J.
Nikon Corporation
Wiesner Leland
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