Pedestal isolated junction structure and method of manufacture

Details Pedestal isolated junction structure and method of manufacture Pedestal isolated junction structure and method of manufacture

1997-12-04

1999-10-26

Booth, Richard

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438411, 438421, 438422, H01L 21336

Patent

active

059727586

ABSTRACT:
A MOSFET structure in which the channel region is contiguous with the semiconductor substrate while the source and drain junctions are substantially isolated from the substrate, includes a dielectric volume formed adjacent and subjacent to portions of the source and drain regions.
In a further aspect of the invention, a process for forming an isolated junction in a bulk semiconductor includes forming a dielectric volume adjacent and subjacent to portions of the source and drain regions.

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patent: 5885876 (1997-07-01), Dennen
Lin et al, "Polysilicon gate depletion effect on deep-submicron circuit performance," IEEE NUPAD V pp. 185-188, 1994.
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Liang et al, "An analytical model for self-limiting behavior of hot-carrier degradation in 0.25 micron nMOSFET's," IEEE Electron Device Letters, vol. 13, No. 11, pp. 569-571, Nov. 1992.
Gautier et al "Body charge related transient effects in floating body SOI NMOSFET's" IEEE IEDM pp. 623-626, 1995.
Chauet al, "Scalability of Partially depleted SOI technology for sub 0.25 micron logic applications," IEEE IEDM 97 pp. 591-594, 1997.
Sinitsky, et al, "AC output conductance of SOI MOSFET's and impact on analog applications," IEEE Electron Device Letters vol. 18, No. 2, pp. 36-38, 1997.

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