PE-SiN spacer profile for C2 SAC isolation window

Details PE-SiN spacer profile for C2 SAC isolation window PE-SiN spacer profile for C2 SAC isolation window

1999-05-03

2001-05-01

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S199000, C438S253000, C438S396000, C438S705000, C438S706000, C438S734000, C438S744000

Reexamination Certificate

active

06225203

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of improving the SiN spacer profile in the process of forming a self-aligned contact opening in the fabrication of integrated circuits.
(2) Description of the Prior Art
The self-aligned contact (SAC) technology has been widely adopted to reduce device area in the fabrication of integrated circuit devices. For example, in forming a SAC for a capacitor between bit lines, the bit lines having silicon nitride spacers on their sidewalls are formed over an insulating layer. A silicon oxide layer covers the bit lines and silicon nitride spacers. A contact opening is etched through the silicon oxide layer to the underlying node contact region. The contact is self-aligned because the silicon nitride spacers are not etched by the silicon oxide etch and thereby form the contact opening.
Typically, a low-pressure furnace deposition is used for the silicon nitride spacer material (LP-SiN) at a temperature of about 800° C. However, for embedded dynamic random access memory (DRAM) devices, it is desirable to reduce the thermal budget to minimize the impact on the titanium silicide in the logic region. Therefore, it is desirable to deposit the silicon nitride spacer material by plasma-enhanced chemical vapor deposition. This presents the problem of how to etch the silicon nitride to form spacers having a good profile.
U.S. Pat. 5,766,992 and 5,731,236, both to Chou et al disclose a PECVD silicon nitride layer etched using SF
6
or CHF
3
to form spacers. U.S. Pat. No. 5,776,832 to Hsieh et al teaches using CHF
3
to etch an opening through a dielectric layer.
SUMMARY OF THE INVENTION
Accordingly, it is a principal object of the present invention to provide an effective and very manufacturable method of forming a silicon nitride spacer having a good profile.
It is a further object of the invention to provide a method of forming a self-aligned contact wherein a silicon nitride spacer of high quality is provided.
Yet another object of the invention is to provide a method of forming a PE-CVD silicon nitride spacer having a good profile in the fabrication of a self-aligned contact.
A still further object is to provide a method of forming a PE-CVD silicon nitride spacer having a good profile in the fabrication of a self-aligned contact wherein a two-step etching process forms the spacer.
In accordance with the objects of this invention a method of forming a PE-CVD silicon nitride spacer having a good profile in the fabrication of a self-aligned contact wherein a two-step etching process forms the spacer is achieved. Semiconductor device structures are formed on a semiconductor substrate. A layer of silicon nitride is deposited by plasma-enhanced chemical vapor deposition over the surface of the substrate and overlying the semiconductor device structures. The silicon nitride layer is etched away using a two-step etching process to leave silicon nitride spacers on the side surfaces of the semiconductor device structures. The two-step process comprises a first etching away of 70 to 85% of the silicon nitride layer using Cl
2
/He chemistry and a second etching away of the remaining silicon nitride on the top surface of the semiconductor device structures using SF
6
/CHF
3
/He chemistry.


REFERENCES:
patent: 5480814 (1996-01-01), Wuu et al.
patent: 5731236 (1998-03-01), Chou et al.
patent: 5766992 (1998-06-01), Chou et al.
patent: 5776832 (1998-07-01), Hsieh et al.
patent: 5914279 (1999-06-01), Yang et al.
patent: 5981369 (1999-10-01), Yoshida et al.
patent: 6037216 (2000-03-01), Liu et al.

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