Patterning methods for fabricating semiconductor devices

Details Patterning methods for fabricating semiconductor devices Patterning methods for fabricating semiconductor devices

2003-01-24

2004-08-17

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

C438S734000

Reexamination Certificate

active

06777345

ABSTRACT:

This application claims the benefit of Korean Patent Application No. 2002-04779, filed on Jan. 28, 2002.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to methods of fabricating semiconductor devices and, more particularly, to patterning methods for fabricating semiconductor devices including a multiple photolithographic process.
2. Discussion of Related Art
Fabrication processes of semiconductor devices can include an ion implantation process for implanting impurities into a semiconductor substrate, a deposition process for forming a material layer, a thermal process for heat-treating at a high temperature, and photolithographic/etching processes for patterning a material layer. However, in the fabrication processes of the semiconductor devices, a process deviation, which represents a degree of variation of process results according to a position on a wafer or to an order of wafers, can be generated. Process deviation can be an important factor in limiting the yield of the semiconductor devices with higher integration semiconductor devices and increased wafer size.
FIGS. 1A and 1B
are diagrams illustrating an influence of a process deviation on characteristics of semiconductor devices.
FIG. 1A
illustrates comparisons between a line width and a process deviation.
FIG. 1B
illustrates a ratio of process deviations to line widths for semiconductor devices.
Due to an industrial need for high integration, techniques for reducing a line width and process deviation have been developed. However, as illustrated in
FIGS. 1A and 1B
, line width has decreased at a greater rate than process deviation.
A process deviation effect r, which represents an influence of the process deviation on characteristics of semiconductor devices, may result in the deterioration of products. The process deviation effect r has increased with time (FIG.
1
B), due to the difference in the rates of advancement for process deviation and line width. The process deviation effect r becomes a design issue that needs to be addressed below a critical process deviation effect r
0
, and thus needs to be considered when designing the characteristics of semiconductor devices. Further, as highly integrated and reliable semiconductor devices have been required, the critical process deviation effect r
0
grows smaller.
FIG. 2
is a process flowchart illustrating a conventional patterning method for fabricating a semiconductor device.
Referring to
FIG. 2
, after preparing n wafers (
10
), a material layer is deposited on the wafers (
11
). Process conditions for patterning the material layer are set (
12
). That is, target line widths (1
0
, 1′
0
) and permissible error ranges (S, S′) for the patterning process are set. 1
0
and S are target values for an inspection step
18
to be performed after a photolithographic process and before an etching process. 1′
0
and S′ are target values for an inspection step
22
to be performed after the etching process.
A surface of each semiconductor substrate is coated with a photoresist layer where the material layer is formed (
13
,
14
). After undergoing exposure and developing processes to form a photoresist pattern (
15
,
16
), a line width 1 of the photoresist pattern is measured (
17
). The line width is compared to the permissible error range (
18
) before the etching process (
19
). The semiconductor substrates are repeatedly coated and etched (
13
-
18
) until a difference between the measured line width 1 and the target line width 1
0
of the photoresist pattern does not depart from the permissible error range S (
18
).
When the line width 1 of the photoresist pattern is within the permissible error range (e.g., |1-1
0
|<S), a preliminary etching process
19
is carried out using the photoresist pattern as an etch mask to form a material pattern. At this time, the preliminary etching process
19
can be applied to one wafer (WF
i
, i=1) selected from the wafers. After removing the photoresist pattern
20
from the wafer (WF
i
, i=1), a line width (1′
i
, i=1) of the material pattern can be measured (
21
).
When a difference between the measured line width 1′
1
and the target line width 1′
i
of the material pattern is within the permissible error range S, a main etching process (
23
) is applied to the remaining wafers. At this time, the main etching process
23
is conducted under the same process conditions as the preliminary etching process. As a result, the material layer is etched to form a material pattern. The photoresist pattern is removed to uncover the material pattern (
24
), and a line width 1′
i
of the uncovered material pattern is then measured (
25
).
If the line width 1′
1
of the material pattern that is measured during the preliminary etching process
19
is not within the permissible error range (e.g., |1′-1′
0
|>S′), the photoresist pattern is removed (
32
,
33
) and step
14
(i.e., coating the photoresist layer) through step
22
(i.e., comparing a line width) are repeatedly performed.
As mentioned above, when the line width measured in the comparing step (
18
,
33
) before/after the preliminary etching process
19
departs from the permissible error range, unfavorable rework processes (
30
,
32
, and
33
) need to be performed. As illustrated in
FIGS. 1A and 1B
, as an influence of the process deviation on characteristics of the semiconductor devices increases, the line widths measured before/after the etching process can become increasingly different. Thus, the number of rework processes (
30
,
32
, and
33
) increases, adding to fabrication costs.
Although problems of the patterning process are explained in relation to a process deviation of a line width by
FIG. 2
, the process deviation may occur during a thermal process and an ion implantation process. That is, characteristics of impurity regions used for source/drain regions of transistors are varied according to positions in wafers, due to process deviations of the thermal process and the ion implantation process. The characteristic of the impurity region is an important variable for determining product characteristics of semiconductor devices. Accordingly, the process deviation may cause deterioration of the semiconductor devices. In particular, as illustrated in
FIGS. 1A and 1B
, with a high integration of semiconductor devices, as trends progress the process deviation will surpass the critical process deviation effect r
0
.
Therefore, a need exists for methods for preventing or correcting deterioration of products caused by the process deviation.
SUMMARY OF THE INVENTION
It is therefore a feature of the present invention to provide a method for fabricating a semiconductor device that enables compensation for a process deviation.
It is another feature of the present invention to provide a method for fabricating a semiconductor device that may minimize rework processes during a patterning process.
In accordance with an aspect of the present invention, there is provided a patterning method for fabricating a semiconductor device comprising performing a photolithographic process at least twice in one processing step. The method comprises preparing a wafer having a plurality of independent patterning regions. After forming a predetermined material layer on the wafer, the material layer is patterned to form a material pattern. The patterning process is carried out such that the material patterns have different line widths at a plurality of the independent patterning regions.
Patterning the material layer preferably comprises performing a plurality of photolithographic processes, which are separately applied to each patterning region. At this time, a plurality of the photolithographic processes are preferably applied to each independent patterning region using different reticles. It is also preferable that the reticles have different line widths and identical circuit pattern designs.
Patterning the material layer preferably

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