Patterning method for fabricating high resolution structures

Details Patterning method for fabricating high resolution structures Patterning method for fabricating high resolution structures

2005-12-30

2008-10-21

Garber, Charles D. (Department: 2812)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S161000

Reexamination Certificate

active

07439193

ABSTRACT:
Provided is a patterning method capable of fabricating high resolution structures without using a high resolution patterning step. The method comprises the steps of: (i) pre-patterning a layer of material (12) on a substrate (10), (ii) spin-coating a solution of a film-forming substance over the pre-patterned substrate, (iii) drying the spin-coated solution to form a film (14) of the film-forming substance on the unpatterned areas of the substrate and on the surface and sides of the pre-patterned material, (iv) etching the dried film in such a way that it remains only around the sides of the pre-patterned material, and (v) removing the pre-patterned material to leave ridges (20) of the film-forming substance on the substrate, the pattern of the ridges corresponding to the outline of the pre-patterned material.A metal layer may then be deposited on the resulting patterned substrate followed by removal of the ridges leaving discrete areas of metal which form latent source and drain electrodes of a thin film transistor. An array of thin film transistors may then be formed by selectively depositing areas of semiconductor, insulator and conductor, the latter forming a gate electrode associated with each pair of source and drain electrodes.

REFERENCES:
patent: 4359816 (1982-11-01), Abbas et al.
patent: 4784718 (1988-11-01), Mitani et al.
patent: 5147740 (1992-09-01), Robinson
patent: 6183938 (2001-02-01), Lyons et al.
patent: 6383952 (2002-05-01), Subramanian et al.
patent: 6566280 (2003-05-01), Meagley et al.
patent: 2002/0155389 (2002-10-01), Rangarajan et al.
patent: 2004/0029382 (2004-02-01), Kawase
patent: 2004/0201011 (2004-10-01), Sakurada et al.
patent: A 58-145133 (1983-08-01), None
patent: A 60-066432 (1985-04-01), None
patent: A 06-188288 (1994-07-01), None
patent: WO 2004/013922 (2004-02-01), None

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