Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-05-01
2007-05-01
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C430S030000
Reexamination Certificate
active
10920397
ABSTRACT:
A method of correcting a finish pattern dimension by using OPC when a design pattern is formed on a wafer, including selecting and determining a first design pattern included in the design pattern; acquiring a measurement value of a first finish pattern dimension when the first design pattern is formed on a wafer; determining a first calculation model by using the first finish pattern dimension; selecting and determining a second design pattern from the design pattern except for the first design pattern; performing first simulation by using the first calculation model, and calculating a second finish pattern dimension when the second design pattern is formed on a wafer; determining a second calculation model for performing second simulation which is faster than the first simulation, by using the first and second finish pattern dimensions; and performing the second simulation by using the second calculation model, and calculating a third finish pattern dimension of a third design pattern of the design pattern except for the first and second design patterns.
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Kotani Toshiya
Nojima Shigeki
Dimyan Magid Y.
Siek Vuthe
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