Pattern controlled IC layout

Details Pattern controlled IC layout Pattern controlled IC layout

2011-06-28

2011-06-28

Cho, James (Department: 2819)

Electronic digital logic circuitry

Significant integrated structure, layout, or layout...

C326S104000, C257S206000

Reexamination Certificate

active

07969199

ABSTRACT:
The invention provides a reduced complexity layout style based on applying a limited set of changes to an underlying repeated base template. With the templates properly defined in accordance with the characteristic features disclosed, the invention enables efficient implementation of logic circuitry, with a dramatic reduction in the pattern complexity (or number of unique layout patterns at each mask level) for realistically sized designs. This reduction in pattern complexity that the invention provides is particularly important for advanced and emerging semiconductor processes, because it enables effective use of SMO and full-chip mask optimization.

REFERENCES:
patent: 5796129 (1998-08-01), Mizuno
patent: 7446352 (2008-11-01), Becker
patent: 7465973 (2008-12-01), Chang
patent: 7627849 (2009-12-01), Gupta
patent: 7667254 (2010-02-01), Yamamoto
patent: 7676772 (2010-03-01), Nakagawa
patent: 7743349 (2010-06-01), Gupta
patent: 7745239 (2010-06-01), Nakagawa
patent: 7763534 (2010-07-01), Smayling
patent: 7888705 (2011-02-01), Becker et al.
patent: 2008/0137051 (2008-06-01), Maly
patent: 2010/0001321 (2010-01-01), Becker
patent: 2010/0006897 (2010-01-01), Becker
patent: 2010/0006898 (2010-01-01), Becker
patent: 2010/0006899 (2010-01-01), Becker
patent: 2010/0006900 (2010-01-01), Becker
patent: 2010/0006901 (2010-01-01), Becker
patent: 2010/0006902 (2010-01-01), Becker
patent: 2010/0006903 (2010-01-01), Becker
patent: 2010/0006947 (2010-01-01), Becker
patent: 2010/0006948 (2010-01-01), Becker
patent: 2010/0006950 (2010-01-01), Becker
patent: 2010/0006951 (2010-01-01), Becker
patent: 2010/0006986 (2010-01-01), Becker
patent: 2010/0011327 (2010-01-01), Becker
patent: 2010/0011328 (2010-01-01), Becker
patent: 2010/0011329 (2010-01-01), Becker
patent: 2010/0011330 (2010-01-01), Becker
patent: 2010/0011331 (2010-01-01), Becker
patent: 2010/0011332 (2010-01-01), Becker
patent: 2010/0011333 (2010-01-01), Becker
patent: 2010/0012981 (2010-01-01), Becker
patent: 2010/0012982 (2010-01-01), Becker
patent: 2010/0012983 (2010-01-01), Becker
patent: 2010/0012984 (2010-01-01), Becker
patent: 2010/0012985 (2010-01-01), Becker
patent: 2010/0012986 (2010-01-01), Becker
patent: 2010/0017766 (2010-01-01), Becker
patent: 2010/0017767 (2010-01-01), Becker
patent: 2010/0017768 (2010-01-01), Becker
patent: 2010/0017769 (2010-01-01), Becker
patent: 2010/0017770 (2010-01-01), Becker
patent: 2010/0017771 (2010-01-01), Becker
patent: 2010/0017772 (2010-01-01), Becker
patent: 2010/0019280 (2010-01-01), Becker
patent: 2010/0019281 (2010-01-01), Becker
patent: 2010/0019282 (2010-01-01), Becker
patent: 2010/0019283 (2010-01-01), Becker
patent: 2010/0019284 (2010-01-01), Becker
patent: 2010/0019285 (2010-01-01), Becker
patent: 2010/0019286 (2010-01-01), Becker
patent: 2010/0019287 (2010-01-01), Becker
patent: 2010/0019288 (2010-01-01), Becker
patent: 2010/0023906 (2010-01-01), Becker
patent: 2010/0023907 (2010-01-01), Becker
patent: 2010/0023908 (2010-01-01), Becker
patent: 2010/0023911 (2010-01-01), Becker
patent: 2010/0025731 (2010-02-01), Becker
patent: 2010/0025732 (2010-02-01), Becker
patent: 2010/0025733 (2010-02-01), Becker
patent: 2010/0025734 (2010-02-01), Becker
patent: 2010/0025735 (2010-02-01), Becker
patent: 2010/0025736 (2010-02-01), Becker
patent: 2010/0032721 (2010-02-01), Becker
patent: 2010/0032722 (2010-02-01), Becker
patent: 2010/0032723 (2010-02-01), Becker
patent: 2010/0032724 (2010-02-01), Becker
patent: 2010/0032726 (2010-02-01), Becker
patent: 2010/0037194 (2010-02-01), Becker
patent: 2010/0037195 (2010-02-01), Becker
patent: 2010/0096671 (2010-04-01), Becker
patent: 2010/0187615 (2010-07-01), Becker
patent: 2010/0187616 (2010-07-01), Becker
patent: 2010/0187617 (2010-07-01), Becker
patent: 2010/0187618 (2010-07-01), Becker
patent: 2010/0187619 (2010-07-01), Becker
patent: 2010/0187620 (2010-07-01), Becker
patent: 2010/0187621 (2010-07-01), Becker
patent: 2010/0187622 (2010-07-01), Becker
patent: 2010/0187623 (2010-07-01), Becker
patent: 2010/0187624 (2010-07-01), Becker
patent: 2010/0187625 (2010-07-01), Becker
patent: 2010/0187626 (2010-07-01), Becker
patent: 2010/0187627 (2010-07-01), Becker
patent: 2010/0187628 (2010-07-01), Becker
patent: 2010/0187630 (2010-07-01), Becker
patent: 2010/0187631 (2010-07-01), Becker
patent: 2010/0187632 (2010-07-01), Becker
patent: 2010/0187633 (2010-07-01), Becker
patent: 2010/0187634 (2010-07-01), Becker
T. Jhaveri, “Regular Design Fabrics for Low Cost Scaling of Integrated Circuits,” Ph.D. Thesis, Carnegie-Mellon University (2010).
T. Jhaveri, “Improvements in Integrated Circuit Patterning Through Extreme Layout Regularity,” M.S.E.E. Thesis, Carnegie-Mellon University (2007).
L. Leibmann, et al., “Simplify to Survive, prescriptive layouts ensure profitable scaling to 32nm and beyond,” Proc. SPIE, vol. 7275, 72750A (2009).
T. Jhaveri, et al., “Layout Pattern Minimization for Next-Generation Technologies,” Proc. SPIE, vol. 7641 (2010).
T. Jhaveri, et al., “OPC Simplification and Mask Cost Reduction Using Regular Design Fabrics,” Proc. of SPIE vol. 7274 (2009).
R. Socha, et al., “Design Compliant Source Mask Optimization (SMO),” Proc. of SPIE vol. 7748 (2010).
L. Liebmann, et a., “Demonstrating the Benefits of Template-based Design-technology Co-optimization,” Proc. of SPIE, vol. 7641 (2010).
T. Jhaveri, et al., “Economic Assessment of Lithography Strategies for the 22nm Technology Node,” Proc. of SPIE, vol. 7488 (2009).
T. Jhaveri, et al., “Maximization of layout printability/manufacturability by extreme layout regularity,” J. Micro/Nanolith. MEMS MOEMS 6(3), Jul.-Sep. 2007.
T. Jhaveri, et al., “Enabling Technology Scaling with ‘In Production’ Lithography Processes,” Proceedings of the SPIE, vol. 6924 (2008).
B. Taylor, “Automated Layout of Regular Fabric Bricks,” M.S. Thesis, Carnegie-Mellon University (2005).

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