Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2009-09-03
2011-10-18
Pham, Thanhha (Department: 2894)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S192000, C257S369000, C257SE27062
Reexamination Certificate
active
08039903
ABSTRACT:
In various embodiments, a tiered gate structure transistor is provided including a source, a drain, and a gate between the source and the drain. The tiered gate structure transistor including a gate foot having a top portion and sidewalls. A gate head is attached to the top portion of the gate foot. A passivation layer extends along and directly contacts an uppermost surface of the source, and extends along and directly contacts an uppermost surface of the drain, the passivation layer surrounds the sidewalls of the gate foot such that the top portion is not covered by the passivation layer and such that the passivation layer surrounding the sidewalls supports the gate head.
REFERENCES:
patent: 5053348 (1991-10-01), Mishra et al.
patent: 5500381 (1996-03-01), Yoshida et al.
patent: 5693548 (1997-12-01), Lee et al.
patent: 5770525 (1998-06-01), Kamiyama
patent: 5981319 (1999-11-01), Lothian et al.
patent: 6051454 (2000-04-01), Anda et al.
patent: 6204102 (2001-03-01), Yoon et al.
patent: 6294446 (2001-09-01), Ishikawa
patent: 6387783 (2002-05-01), Furukawa et al.
patent: 6417084 (2002-07-01), Singh et al.
patent: 6737202 (2004-05-01), Gehoski et al.
patent: 7041541 (2006-05-01), Behammer
patent: 7387955 (2008-06-01), Ahn et al.
patent: 7439166 (2008-10-01), Milosavljevic et al.
patent: 7534672 (2009-05-01), Milosavljevic et al.
patent: 7723761 (2010-05-01), Milosavljevic et al.
patent: 2003/0119233 (2003-06-01), Koganei
patent: 2004/0063303 (2004-04-01), Behammer
patent: 2004/0082158 (2004-04-01), Whelan et al.
patent: 2004/0104443 (2004-06-01), Ahn et al.
patent: 2007/0134862 (2007-06-01), Lim et al.
R. Grundbacher, I. Adesida, Y.C. Kao, A.A. Ketterson, Single step lithography for double-recessed gate pseudomorphic electron mobility transistors, J. Vac. Sci. Technol. B 15 (1), pp. 49-52, American Vacuum Society, Jan./Feb. 1997.
USPTO Notice of Allowance and Fees Due, mailed Jan. 27, 2010 for U.S. Appl. No. 12/212,627, filed Sep. 17, 2008, Inventor Milosavljevic.
Antcliffe Michael
Hodgson Lorna
Hu Ming
Milosavljevic Ivan
Schmitz Adele
Balzan Christopher R.
HRL Laboratories LLC
Pham Thanhha
LandOfFree
Passivated tiered gate structure transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Passivated tiered gate structure transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Passivated tiered gate structure transistor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4259859