Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
1997-09-30
2002-03-19
Yoo, Do Hyun (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S147000, C711S153000, C711S151000, C711S170000
Reexamination Certificate
active
06360303
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to computing systems in which multiple processor units share a single memory to form a distributing processing system. In particular, the invention relates to partitioning the shared memory so that each processor unit has exclusive access to an associated memory partition.
The reliance on computer systems permeates our society. As more services move on-line, continuous availability and accessibility becomes a need rather than just a luxury. One approach to meeting this need are present fault tolerant architectures structured to provide highly available, fault tolerant, and scalable systems.
Many computing systems today are structured to perform on-line transaction processing (OLTP). OLTP is found in a number of commercial applications such as, for example, financial transactions (e.g., coordinating the interchange of automated teller machines), tracking data for companies, tracking manufacturing parts (e.g., automobile parts), and many other like functions. In order to increase the number of transactions capable of being processed at any moment in time, multiple processor system architectures are used.
Among the advantageous provided by multiple processor architectures are the capability of allocating transaction functions to more than one processor unit. (A transaction may be viewed as a programmatic construct that is an explicitly delimited operation, or set of related operations, for making a change to the content of a database from one consistent state to another.) Often, a transaction may require related “services” before the transaction is completed, and a multiple processor system provides the hardware platform for executing these services in parallel, permitting the transaction to complete much faster. The second advantage is that a multiple processor architecture lends itself to providing continuous availability, i.e., fault tolerance.
Recent approaches to fault tolerant computing has been extended to include groups of individual processor units to operate as a symmetric multiprocessing (SMP) system. This approach exploits the power of multiple processor units through distribution of the operating system across the processor units that comprise the SMP system, thereby balancing the system load of the SMP configuration. In addition, an SMP configuration can reduce downtime because the operating system can continue to run on remaining processor units in the event one the processor units should fail.
A hallmark of SMP systems is that the processor units that make up the system share a single (main) memory. This can create a drag on the overall performance of the SMP system, as well as impede scalability, when multiple processes, running on the multiple processor units, desire or require memory access. For example, when a process running one of the processors of an SMP system seeks access to the shared memory at substantially the same time as another process running on another one of the processor units, memory conflicts can arise to the harm of system performance. As noted, a transaction will often require the use of a number of the services provided by parallel (or seemingly so) execution of processes running on, or available to, the SMP system. For example, a transaction to change a bank account may require, in simplistic form, a database management process to make the access and effect the change, a disk processes make the actual access to the file in which the change is to be made, and a reporting process to inform the user of the status of the change. Fault tolerance in transaction processing requires that the state of the transaction be monitored at all times, and this, in turn, necessitates one or more logs to list which processes have been called into play to execute the transaction, and the processor unit of the SMP system on which the process is executing, the state of completion of each process, and other information describing the execution of the transaction. This information and more is needed in order that a decision be made as to whether the transaction can be completed or unraveled to attempt it again should a failure of a process, a processor unit, or some other element of the system occur.
In reality, transaction processing will call into play numerous services, so that state tracking can become enormous. This, in turn, will require the processor units of the SMP system to initiate diverse memory operations, often to the same tables and/or data structures. Thus, when one processor unit has accessed a table that is needed by another processor unit, the later processor unit must wait until the earlier access is complete. When many transactions are executing on an SMP system, this waiting for memory resource can place a drag on performance.
Another drawback of the memory sharing in a SMP systems is encountered when processor units are added to the system in an effort to improve performance. Any piece of the shared memory that can be accessed by any process running on any processor unit of the SMP system can become a bottleneck if access must be mutually exclusive. Adding processor units has been found an inefficient and unsatisfactory solution because it does not attack the problem of the bottleneck. In fact, adding processor units can tend to exacerbate the bottleneck problem because now accesses to the same tables have been increased. Accordingly, something more is needed in order to be able to take full advantage of features offered by SMP architectures.
SUMMARY OF THE INVENTION
The present invention is directed to a technique that operates to alleviate the bottleneck created by shared memory SMP architectures. The invention provides a method of partitioning a shared memory so that the individual processor units of a SMP system each have exclusive use of a corresponding memory partition.
According to a preferred embodiment of the invention, each processor unit of an SMP system will continue to have shared access to an area of the shared memory element. However, a portion of the memory element is partitioned into separate memory segments, one for each of the processor units of the SMP system. The remaining portion of the memory element (i.e., that portion not allocated to the memory segments) is shared by the processor units. Accordinng to the invention there is established a memory segment address table having entries corresponding to each processor unit of the system. Next, a memory segment is allocated for each processor unit and the location address of that memory segment is written to the memory segment address table at the entry corresponding to such processor unit. Frequently accessed tables and dynamic data structures are kept in the corresponding memory partitions. When an application is first called to be executed on the system, the application is assigned to execute on one of the processor units. At that time the affinity of the process is set for the corresponding processor unit on which it first executes, allowing it access to the memory segment associated with the processor unit. Subsequent executions of the process will be on the same processor unit, permitting the process to leave in the memory segment tables and/or other data structures without fear that they will be somehow corrupted by other processes running on other processor systems. The process executing on a one of the processor units of the SMP system needing to access one of these tables/data structures will be given information identifying the location of the corresponding memory segment for the processor unit.
In a further embodiment of the invention, each memory segment has a locking mechanism that provides an executing process (actually, threads of the process) with mutual exclusive access to the memory segment to reduce conflict. A data structure associated with each locking mechanism will contain information as to the identity of the process then accessing the memory segment, if any. If no process is currently accessing the memory segment, it is available. The locking mechanism includes provision, however, of nest
Cheung Yu-Cheung
Johnson Charles W.
Wisler David
Compaq Computer Corporation
McLean Kimberly
Oppenheimer Wolff & Donnelly
Sherry Leah
Yoo Do Hyun
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