Partially distributed control mechanism for scanout...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Details

C714S027000, C714S727000, C713S500000

Reexamination Certificate

active

06973606

ABSTRACT:
The invention includes an integrated circuit (IC). The IC includes an internal test bus (ITB). The IC also includes a number of deskew clusters connected to the ITB. The deskew clusters each include a deskew controller. The IC also includes an integrated test controller (ITC) connected to the ITB. Further, the IC includes a debug unit connected to the ITC. The ITC generates a single global control signal and the deskew controller generates a first local command signal.

REFERENCES:
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patent: 5701308 (1997-12-01), Attaway et al.
patent: 5790561 (1998-08-01), Borden et al.
patent: 5951696 (1999-09-01), Naaseh et al.
patent: 6181151 (2001-01-01), Wasson
patent: 6665816 (2003-12-01), Edwards et al.

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