Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-12-06
2005-12-06
Lamarre, Guy J. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S027000, C714S727000, C713S500000
Reexamination Certificate
active
06973606
ABSTRACT:
The invention includes an integrated circuit (IC). The IC includes an internal test bus (ITB). The IC also includes a number of deskew clusters connected to the ITB. The deskew clusters each include a deskew controller. The IC also includes an integrated test controller (ITC) connected to the ITB. Further, the IC includes a debug unit connected to the ITC. The ITC generates a single global control signal and the deskew controller generates a first local command signal.
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Intel Corporation
Lamarre Guy J.
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