Partial write control apparatus

Details Partial write control apparatus Partial write control apparatus

1987-05-20

1988-10-18

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

G11C 700, G11C 1140

Patent

active

047792329

ABSTRACT:
In a partial write control apparatus for a memory having a high speed operation mode such as a nibble mode or a page mode, when a partial write request for a plurality of words including those which require partial write is received, a memory control signal generator causes the memory to read successively all the words requiring partial write in a single high speed operation mode read cycle. A merging circuit merges those portions of the read-out words which need no alteration with write data and forms a group of updated complete words. Then, the memory control signal generator causes the memory to write successively these words in a single high speed operation mode write cycle.

REFERENCES:
patent: 4618946 (1986-10-01), Little et al.
patent: 4639894 (1987-01-01), Ishii
patent: 4663735 (1987-05-01), Novak et al.
patent: 4685089 (1987-04-01), Patel et al.

Affiliated with

Also associated with

Rating

Partial write control apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Partial write control apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Partial write control apparatus will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1198967