Partial vertical memory cell and method of fabricating the same

Details Partial vertical memory cell and method of fabricating the same Partial vertical memory cell and method of fabricating the same

2005-11-29

2005-11-29

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S301000, C257S304000

Reexamination Certificate

active

06969881

ABSTRACT:
A partial vertical memory cell and fabrication method thereof. A semiconductor substrate is provided, in which two deep trenches having deep trench capacitors respectively are formed, and the deep trench capacitors are lower than a top surface of the semiconductor substrate. A portion of the semiconductor outside the deep trenches is removed to form a pillar between. The pillar is ion implanted to form an ion-doped area in the pillar corner acting as a S/D area. A gate dielectric layer and a conducting layer are conformally formed on the pillar sequentially. An isolation is formed in the semiconductor substrate beside the conducting layer. The conducting layer is defined to form a first gate and a second gate.

REFERENCES:
patent: 6534359 (2003-03-01), Heo et al.
patent: 6777737 (2004-08-01), Mandelman et al.

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