Parity checking device and method in data communication system

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C712S010000

Reexamination Certificate

active

06718514

ABSTRACT:

PRIORITY
This application claims priority to an application entitled “Parity Checking Device and Method in Data Communication System” filed in the Korean Industrial Property Office on Dec. 29, 1999 and assigned Serial No. 99-65241, the contents of which are hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to an error checking device and method in a data communication system, and in particular, to an error checking device and method using parity checking.
2. Description of the Related Art
A data communication system exchanges data between a transmitter and a receiver. Errors may occur in the exchanged data according to the communication environment between the transmitter and the receiver. Hence, the data communication system needs to check for possible generated errors in the received data and correct them. A popular error checking method is parity checking.
According to a conventional error checking method utilizing parity checking, after data is shifted on a bit basis, it is determined whether a carry (e.g., value “1”) has been generated after the bit shift, and the number of carries are counted. If all the bits of the data are completely shifted, the resulting count value is subjected to modulo-2 addition and it is checked whether the remainder of the modulo-2 addition is “0” or “1” to thereby determine whether the data has errors. Consequently, the conventional parity check method is the process of determining whether data has errors depending on whether the data has an odd or even number of 1s.
FIG. 1
is a flowchart illustrating the conventional parity check method in a data communication system.
Referring to
FIG. 1
, a loop count and a carry count are set to 0s in step
110
and data is shifted by one bit in step
120
. It is determined whether a carry has been generated after the shift in step
130
. Upon generation of a carry, the carry count is increased by 1 in step
140
. If the carry is not generated in step
130
or the carry count is increased in step
140
, the loop count is increased by 1 in step
150
. In step
160
, it is determined whether all the bits of the data have been shifted completely by comparing the loop count with the length of the data. If the loop count is greater than or equal to the data length, it is determined that all the bits of the data have been shifted completely.
If it is determined that all the bits of the data are not shifted in step
160
, steps
120
to
160
are repeated. On the other hand, upon completion of the bit shifts in step
160
, the carry count is modulo-2 added in step
170
. It is determined whether the data has an error based on the remainder of the modulo-2 addition in step
180
. Since the carry count is divided by 2, the remainder is 0 or 1. For example, if the remainder is 1, it may be considered that an error has occurred and if it is 0, it may be considered that the data has no errors.
In the foregoing conventional parity check method, a decision is made as to whether a carry has been generated in a loop at every bit shift of the data. Thus, time required for error check increases in proportion to the number of the bits of the data. For example, if the data has 2
n
bits, the loop must occur 2
n
times.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a parity checking device and method in which a parity check is performed on data for a reduced time in a data communication system.
It is another object of the present invention to provide a parity checking device and method in which a parity check is performed on 2
n
-bit data by repeating a loop (n−1) times (i.e., n loop occurrences) in a data communication system.
It is a further object of the present invention to provide a parity checking device and method utilizing XOR operations in a data communication system.
It is still another object of the present invention to provide a parity checking device and method in which a parity check is performed on data through iterative XOR operations between the upper half bit sequence and lower half bit sequence of the data, and the presence or absence of errors is determined based on the final XOR operation result.
To achieve the above and other objects, there is provided a parity checking device and method in a data communication system. In the parity checking device, a controller determines loop occurring times according to the length of the data and the number of bits to be shifted according to the data or XOR operation results and determines whether the data has an error based on a final XOR operation result. A first register and a second register store the data or the XOR operation results under the control of the controller. A shifter receives the output of the first register and shifts the received bits by the shift bit number received from the controller. An operation unit receives the outputs of the shifter and the second register, performs an XOR operation between the received data from the shifter and second register, and outputs an XOR operation result under the control of the controller.
It is determined whether the data has an error based on a final XOR operation result after as many XOR operations as the loop occurring times are performed.


REFERENCES:
patent: 4462102 (1984-07-01), Povlick
patent: 4486848 (1984-12-01), Kaminski
patent: 5978957 (1999-11-01), Haller et al.
patent: 6094668 (2000-07-01), Oberman
patent: 6108763 (2000-08-01), Grondalski
patent: 6301600 (2001-10-01), Petro et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Parity checking device and method in data communication system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Parity checking device and method in data communication system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Parity checking device and method in data communication system will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3195653

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.