Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2006-04-11
2006-04-11
Baumeister, B. William (Department: 2891)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S612000, C438S614000, C438S622000, C438S623000, C438S624000, C438S626000, C257S707000, C257S737000, C257S738000, C257S778000, C257S780000, C257S758000
Reexamination Certificate
active
07026234
ABSTRACT:
A parasitic capacitance-preventing dummy solder bump structure on a substrate has at least one conductive layer formed on the substrate, a dielectric layer employed to cover the conductive layer, an under bump metallurgy layer (UBM layer) formed on the dielectric layer, and a solder bump formed on the UBM layer.
REFERENCES:
patent: 5220199 (1993-06-01), Owada et al.
patent: 6118180 (2000-09-01), Loo et al.
patent: 6333557 (2001-12-01), Sullivan
patent: 6551856 (2003-04-01), Lee
patent: 6759319 (2004-07-01), Viswanadam et al.
patent: 6847066 (2005-01-01), Tahara et al.
patent: 6913946 (2005-07-01), Lin
patent: 2004/0178436 (2004-09-01), Baniecki et al.
patent: 2004/0183187 (2004-09-01), Yamasaki et al.
patent: 2003017530 (2003-01-01), None
Chen Kuo-Ming
Jao Jui-Meng
Liu Hung-Min
Sheu Shing-Ren
Wang Kun-Chih
Anya Igwe U.
Baumeister B. William
Hsu Winston
United Microelectronics Corp.
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