Parasitic capacitance-preventing dummy solder bump structure...

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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C438S612000, C438S614000, C438S622000, C438S623000, C438S624000, C438S626000, C257S707000, C257S737000, C257S738000, C257S778000, C257S780000, C257S758000

Reexamination Certificate

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07026234

ABSTRACT:
A parasitic capacitance-preventing dummy solder bump structure on a substrate has at least one conductive layer formed on the substrate, a dielectric layer employed to cover the conductive layer, an under bump metallurgy layer (UBM layer) formed on the dielectric layer, and a solder bump formed on the UBM layer.

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patent: 6333557 (2001-12-01), Sullivan
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patent: 6847066 (2005-01-01), Tahara et al.
patent: 6913946 (2005-07-01), Lin
patent: 2004/0178436 (2004-09-01), Baniecki et al.
patent: 2004/0183187 (2004-09-01), Yamasaki et al.
patent: 2003017530 (2003-01-01), None

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