Parameter generating circuit for deciding priority of master...

Details Parameter generating circuit for deciding priority of master... Parameter generating circuit for deciding priority of master...

2006-04-11

2006-04-11

Perveen, Rehana (Department: 2112)

Electrical computers and digital data processing systems: input/

Access arbitrating

C710S244000, C710S116000

Reexamination Certificate

active

07028121

ABSTRACT:
Provided are a parameter generating circuit and a method of generating a parameter which decides priority of master blocks. An arbitration parameter generating circuit includes a counter, a short term arbitration parameter storage unit, a short term reference time measurement unit, a long term arbitration parameter control unit and a long term reference time measurement unit. The counter receives a request signal generated in order for a master block to occupy a system bus and a grant signal generated in order for an arbitrator to allow the master block to occupy the system bus, up-counts when the request signal is at a first logic level, down-counts when the grant signal is at the first logic level, and is reset in response to a predetermined short term reference time signal. The short term arbitration parameter storage unit receives and stores the counted signal as the short term arbitration parameter until the counter is reset in response to the short term reference time signal. The long term arbitration parameter control unit continuously accumulates the short term arbitration parameter outputted from the short term arbitration parameter storage unit, outputs the accumulated short term arbitration parameter as a long term arbitration parameter, and is reset in response to the long term reference time signal.

REFERENCES:
patent: 5241632 (1993-08-01), O'Connell et al.
patent: 5598542 (1997-01-01), Leung
patent: 5778200 (1998-07-01), Gulick
patent: 5862353 (1999-01-01), Revilla et al.
patent: 5862355 (1999-01-01), Logsdon
patent: 5940455 (1999-08-01), Ikeda
patent: 5956493 (1999-09-01), Hewitt et al.
patent: 6088751 (2000-07-01), Jaramillo
patent: 6246256 (2001-06-01), Liu et al.
patent: 6301642 (2001-10-01), Jones et al.
patent: 6704821 (2004-03-01), Scandurra et al.
patent: 6917995 (2005-07-01), Hirose et al.

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