Parallel test system

Details Parallel test system Parallel test system

2007-07-31

2010-10-05

Kerveros, James C (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S738000, C714S741000, C714S742000

Reexamination Certificate

active

07810001

ABSTRACT:
A method and a system for defining groups of tests that may be concurrently performed or overlapped are provided. Channel-independent test groups are determined such that each group includes tests that the input/output channels may be utilized simultaneously without conflicts. The channel-independent test groups are divided into block-under-test (BUT) conflict test groups and total-independence test groups. The total-independence test groups may be performed concurrently. Performance of the BUT-conflict test groups may be overlapped such that the input/output channels are used concurrently, but the execution of the tests by the blocks of the device-under-test (DUT) is performed sequentially.

REFERENCES:
patent: 6966018 (2005-11-01), Hilliges
patent: 6993695 (2006-01-01), Rivoir
patent: 7039545 (2006-05-01), Bundy et al.
patent: 7178074 (2007-02-01), Ushikubo
patent: 7240258 (2007-07-01), Hayes
patent: 7502974 (2009-03-01), Garg et al.
patent: 7550988 (2009-06-01), Schroth et al.

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