Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Patent
1996-12-20
1999-10-05
Tu, Trinh L.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
714820, 714 42, 365201, 370244, G11C 2900, G06F 1100
Patent
active
059616571
ABSTRACT:
There is disclosed a parallel test circuit for a semiconductor memory device having a memory army with a plurality of memory cells and a plurality of comparators used for high-speed memory cell test, including a plurality of fist comparators performing first comparison with respect to data transmitted through a plurality of data output lines formed near memory blocks of the memory array; a plurality of second comparators coupled in common with each output terminal of the first comparators and performing second comparison with respect to output data of the first comparators; a multiplexer multiplexing output of the second comparator; first and second switches alternatively connected to an output terminal of the multiplexer; and a data output buffer coupled in common with output terminals of the first and second switches and buffering outputs of the first and second switches. The multiplexer is connected to the first switches for a first mode operation, and is connected to the second switch for a second mode operation to thereby perform a two-way data test.
REFERENCES:
patent: 5202888 (1993-04-01), Ochiai
patent: 5428575 (1995-06-01), Fudeyasu
patent: 5436911 (1995-07-01), Mori
patent: 5471480 (1995-11-01), You
patent: 5511029 (1996-04-01), Sawada et al.
patent: 5588115 (1996-12-01), Augarten
Jeong Se-jin
Park Chan-Jong
Samsung Electronics Co,. Ltd.
Tu Trinh L.
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