Parallel test circuit for semiconductor memory

Static information storage and retrieval – Read/write circuit – Testing

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

36523008, G11C 700

Patent

active

060260394

ABSTRACT:
A parallel test circuit for a semiconductor memory device includes multiple data input pads, multiple data input buffers respectively connected to the data input pads for receiving write data in response to a chip selection signal during normal operation, and a switching circuit for electrically connecting the data input pads to each other in response to a current leakage test signal applied to the circuit. The circuit enables the detection of leakage current in the input data buffers at the same time that a parallel data writing test is performed, thereby reducing the total time required to test the device.

REFERENCES:
patent: 5559744 (1996-09-01), Kuriyama et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Parallel test circuit for semiconductor memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Parallel test circuit for semiconductor memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Parallel test circuit for semiconductor memory will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1911272

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.