Parallel processing redundancy scheme for faster access times an

Details Parallel processing redundancy scheme for faster access times an Parallel processing redundancy scheme for faster access times an

1995-02-10

1997-05-06

Dinh, Son T.

Static information storage and retrieval

Read/write circuit

Bad bit

371 103, G11C 2900

Patent

active

056277865

ABSTRACT:
A parallel processing redundancy memory circuit. The circuit includes parallel data paths for regular memory columns and redundant columns. An input/output buffer is coupled to the parallel paths and receives I/O selection bits. In operation, address drivers simultaneously access both the regular memory and the redundant columns. The input/output buffer then selects the appropriate data path, as determined by the I/O selection bits, for writing or reading data.

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