Parallel processing for decoding and cyclic redundancy...

Details Parallel processing for decoding and cyclic redundancy... Parallel processing for decoding and cyclic redundancy...

2005-02-23

2008-12-02

Chaudry, Mujtaba K (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S795000

Reexamination Certificate

active

07461324

ABSTRACT:
Depending on the sequence of the decoded payload signal bits (am1, . . . , amA) and redundancy checking bits (pm1, . . . , pmL) which are produced by the Viterbi traceback, either some of these bits are inserted by means of a distribution device (1) from the front into a linear feedback shift register (10), or some of these bits are inserted by means of the distribution device (1) from the rear into a linear feedback shift register (10), or all of them are inserted into a linear feedback shift register (20) from the rear with the allocated coefficients being unchanged, or all of them are inserted into a shift register from the front with the allocated coefficients being inverted. This allows a redundancy checking process to be carried out on a transmitted data block in the shift register (10; 20) without temporary storage of the bits produced by the decoding process.

REFERENCES:
patent: 5090035 (1992-02-01), Murase
patent: 5103451 (1992-04-01), Fossey
patent: 5390189 (1995-02-01), Tateishi
patent: 5748652 (1998-05-01), Kim
patent: 5920593 (1999-07-01), Perl et al.
patent: 6041433 (2000-03-01), Kamada
patent: 6327691 (2001-12-01), Huang
patent: 7088792 (2006-08-01), Rick
patent: 0 052 357 (1987-04-01), None
patent: 1 011 201 (2000-06-01), None
patent: 1 211 813 (2002-06-01), None
patent: 1211813 (2002-06-01), None
“4-Bit Bidirectional Universal Shift Register”, 54F/74F194, National Semiconductor, Nov. 1994, 7 pgs.
XP002255882 “Error Control Coding: Fundamentals and Applications”, Shu Lin and D.J. Costello, 1987, Prentice Hall, Englewood Cliffs, pp. 98-103.
“A Reconfigurable Linear Feedback Shift Register (LFSR) for the Bluetooth System”, P. Kitsos, N. Sklavos, N. Zervas and O. Koufopavlou, VLSI Design Laboratory, University of Patras, IEEE, vol. 2, Sep. 2, 2001, pp. 991-994.
3rdGeneration Partnership Project (3GPP); Technical Specification Group Radio Access Network Multiplexing and Channel Coding (FDD) (3G TS 25.212 version 3.0.0), XP-002149187, Oct. 1999, 54 pgs.
International Search Report, Int'l Application No. PCT/DE03/02111, Int'l Filing Date Jun. 25, 2003, 3 pgs.

Affiliated with

Also associated with

Rating

Parallel processing for decoding and cyclic redundancy... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Parallel processing for decoding and cyclic redundancy..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Parallel processing for decoding and cyclic redundancy... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4035599