Parallel plane substrate

Details Parallel plane substrate Parallel plane substrate

2003-02-21

2003-10-14

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S737000, C438S761000

Reexamination Certificate

active

06632734

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to apparatus and methods for fabricating a conductive substrate. In particular, the present invention relates to a laminated substrate, formed from alternating conductive and dielectric material layers, which may be used as an interposer.
2. State of the Art
Higher performance, lower cost, increased miniaturization of integrated circuit components, and greater packaging density are ongoing goals of the computer industry. As these goals are achieved, microelectronic dice become smaller. A smaller size allows more microelectronic dice to be produced on each semiconductor wafer, which reduces the cost of each microelectronic die. However, the small size of each microelectronic die makes it difficult to directly incorporate them into microelectronic devices. Thus, a microelectronic die may be attached to an interposer to allow for easier connection of the microelectronic die to other device components.
FIG. 18
illustrates a package
200
comprising a microelectronic die
202
electrically connected to an interposer
204
. The interposer
204
comprises a substrate core
206
(e.g., bismaleimide triazine resin, FR4, polyimide materials, and the like) having dielectric layers (e.g., epoxy resin, polyimide, bisbenzocyclobutene, and the like) and conductive traces (e.g., copper, aluminum, and the like) on a top surface thereof to form a top trace network
212
, and dielectric layers and conductive traces on a bottom surface thereof to form a bottom trace network
214
. To achieve electrical interconnect between the top trace-network
212
and the bottom trace network
214
, holes are drilled through the substrate core
206
in specific locations and these holes are plated with a conductive material. The resulting plated holes are known in the art as “plated through-hole (PTH)” vias
218
.
FIG. 19
illustrates the interposer
204
with the top trace network
212
and the bottom trace network
214
on the substrate core
206
. The top trace network
212
comprises a first dielectric layer
222
having first conductive traces
224
formed thereon, wherein the first conductive traces
224
extend through the first dielectric layer
222
to contact the PTH vias
218
or traces
226
which contact the PTH vias
218
. A second dielectric layer
222
′ is disposed over the first dielectric layer
222
and the first conductive traces
224
. Second conductive traces
224
′ are formed on the second dielectric layer
222
′, wherein the second conductive traces
224
′ extend through the second dielectric layer
222
′ to contact a respective first conductive trace
224
. A third dielectric layer
222
″ is disposed over the second dielectric layer
222
′ and the second conductive traces
224
′, and first solder ball lands
228
are formed to extend through the third dielectric layer
222
″. A first solder resist
232
is formed over the third dielectric layer
222
″ to surround the first solder ball lands
228
. The bottom trace network
214
is formed in a similar fashion as the top trace network
212
with first, second, and third dielectric layers (
234
,
234
′, and
234
″, respectively) and first, second, and third conductive traces (
236
,
236
′, and
236
″, respectively), wherein second solder ball lands
238
are formed with the third conductive traces
236
″ and a second solder resist
242
is formed over the third dielectric layer
234
″ and a portion of the third conductive trace
236
″ to surround the second solder ball lands
238
.
Referring to
FIG. 18
, the microelectronic die
202
is attached to and in electrical contact with the top trace network
212
through small solder balls
244
. The small solder balls
244
extend between contacts
246
on the microelectronic die
202
and the first solder ball lands
228
(see FIG.
19
). External contacts
248
(shown as solder balls) are formed on the second solder ball lands
238
(see FIG.
19
). The external contacts
248
are attached to an external electrical system (not shown). Thus, the use of the interposer
204
allows electrical communication between the microelectronic die
202
and external electrical system (not shown)
FIGS. 20-24
illustrate a panel plating, method of forming a copper plated through-hole via, such as shown as the PTH vias
218
in
FIGS. 18 and 19
. As shown in
FIG. 20
, a first copper layer
252
disposed on a first surface
254
of the substrate
206
and a second copper layer
256
disposed on a second surface
258
of substrate
206
. A hole
262
is drilled through the first copper layer
252
, the substrate
206
, and the second copper layer
256
, as shown in FIG.
21
. As shown in
FIG. 22
, a copper sidewall layer
264
is formed on a sidewall(s)
266
of the hole
262
with an electrodeless copper plating technique followed by a copper electroplatin process, as known in the art. A resist layer
268
is patterned over the hole
262
(see
FIG. 22
) and a portion of the first copper layer
252
and the second copper layer
256
, as shown in as FIG.
23
. The first copper layer
252
and the second copper layer
256
are then etched and the resist layer
268
is removed to form a plated through-hole via
218
, as illustrated in FIG.
24
.
The fabrication of the interposer
204
requires a number of processing steps which increases the cost of the package. In particular, the formation of the PTH vias
218
has numerous, time-intensive processing steps. Therefore, it would be advantageous to design an interposer and a technique for fabrication the same which eliminates the need for forming PTH vias.


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R.H. Reynolds, “Microthin-Microordinate Circuit Board,” IBM Technical Disclosure Bulletin, vol. 9, No. 3, Aug. 1, 1966, pp. 250-251, XP002196415, New York, USA.
“Circuitry Device for Dense First and Second Level Packaging,” IBM Technical Disclosure Bulletin, vol. 31, No. 4, Sep. 1, 1988, pp. 222-224, XP000021608, ISSN: 0018-8689, New York, USA.

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