Parallel path alignment method and apparatus

Details Parallel path alignment method and apparatus Parallel path alignment method and apparatus

2008-05-13

2008-05-13

Cao, Chun (Department: 2115)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C365S233100

Reexamination Certificate

active

11047293

ABSTRACT:
A method for aligning parallel path data bit streams that may contain skewed data between bit streams and an integrated circuit are disclosed. The method includes, for each bit stream, sampling P data presented on a positive edge of a clock, sampling N data presented on a negative edge of the clock, and delaying the sampled P and N data by one of zero, one-half, one, or other multiple of one-half clock cycle. Delaying the sampled P and N data by one of zero, one-half, one, or other multiple of one-half clock cycle is selected to remove any skew and aligns the sampled P and N data between bit streams.

REFERENCES:
patent: 6898722 (2005-05-01), Anzai
patent: 2003/0046618 (2003-03-01), Collins
Lammers, David; “RapidIO gains chip support, legitimacy”; EETimes; Apr. 3, 2003; 4 pages; EETimes.
Bouvier, Dan; “The Embedded System Interconnect”; RapidIO: The Interconnect Architecture for High Performance Embedded Systems; Jan. 3, 2003; pp. 1-20 (plus cover and end pages); www.rapidio.org.

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