Parallel input/output self-test circuit and method

Details Parallel input/output self-test circuit and method Parallel input/output self-test circuit and method

2006-05-04

2008-11-04

Louis-Jacques, Jacques (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C370S241000, C375S376000, C375S326000, C375S328000

Reexamination Certificate

active

07447958

ABSTRACT:
A parallel data transmission test system can include a receiver section (100) having input selector circuits (104-O to104-N) that provide a received test data to logic adjust circuits (106-O to106-N) that “logically align” multiple incoming test values to remove intentionally introduced logic difference (e.g., inversion) with respect to one another. Result combining circuit (108) can logically combine output data values and provide a resulting sequence to a pattern sequence test circuit (110).

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