Parallel electronic architecture comprising a plurality of...

Details Parallel electronic architecture comprising a plurality of... Parallel electronic architecture comprising a plurality of...

2005-02-22

2005-02-22

Gaffin, Jeffrey (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Concurrent input/output processing and data transfer

C710S030000

Reexamination Certificate

active

06859847

ABSTRACT:
The parallel electronic architecture comprises a plurality of processor units connected to a communication bus and each adapted to execute one or more predefined tasks automatically. Each processor unit is configured so that each of its tasks is associated with a header, each processor unit is adapted to communicate with the other processor units using the following protocol: sending on the bus a message including a header characterizing a function, and possibly a frame consisting of one or more words, and each processor unit is adapted to decode each header on the bus and, as a function of the value of said header, either to ignore the message on the bus or to execute the task associated with the header of said message.

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patent: 6725281 (2004-04-01), Zintel et al.
patent: 0200447 (1986-05-01), None

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