Parallel data communication having multiple sync codes

Details Parallel data communication having multiple sync codes Parallel data communication having multiple sync codes

2005-07-19

2005-07-19

Lee, Thomas (Department: 2115)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

C713S600000, C714S707000

Reexamination Certificate

active

06920576

ABSTRACT:
A high-speed parallel-data communication approach overcomes skewing problems by transferring digital data with automatic realignment. In one example embodiment, a parallel bus has parallel bus lines adapted to transfer digital data from a data file, along with a synchronizing clock signal. To calibrate the synchronization, the sending module transfers synchronization codes which are sampled and validated according to an edge of the clock signal by a receiving module and then used to time-adjust the edge of the clock signal relative to the synchronization codes. The synchronization codes are implemented to toggle the bus lines with each of the synchronization codes transferred.

REFERENCES:
patent: 5978419 (1999-11-01), Cassiday et al.
patent: 6079035 (2000-06-01), Suzuki et al.
patent: 6725388 (2004-04-01), Susnow
patent: 11074945 (1999-03-01), None
IBM, Enhanced Means for Parallel Synchronization in Crossbar Switching Networks, Jun. 1, 1989, vol. 32, Issue 1, pp. 281-283.

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