Parallel compression test circuit of memory device

Details Parallel compression test circuit of memory device Parallel compression test circuit of memory device

2007-03-06

2007-03-06

Le, Don (Department: 2819)

Electronic digital logic circuitry

With test facilitating feature

C365S201000, C714S718000

Reexamination Certificate

active

11008298

ABSTRACT:
A parallel compression test circuit of a memory device disperses peak current and reduce noise by operating input/output amplifiers at different timings in a parallel compression test mode. The parallel compression test circuit comprises an input/output amplification control unit for activating a plurality of input/output amplifiers connected to a selected bank in a normal mode, and activating the plurality of input/output amplifiers in each bank at different timings in a test mode.

REFERENCES:
patent: 5185744 (1993-02-01), Arimoto et al.
patent: 5475692 (1995-12-01), Hatano et al.
patent: 5717701 (1998-02-01), Angelotti et al.
patent: 6026505 (2000-02-01), Hedberg et al.
patent: 6466490 (2002-10-01), Nagai et al.
patent: 6484289 (2002-11-01), Hsu
patent: 6590799 (2003-07-01), Rickes et al.
patent: 6693841 (2004-02-01), Roohparvar et al.
patent: 6798701 (2004-09-01), Yamazaki
patent: 2003/0071649 (2003-04-01), Dankowski et al.
patent: 2004/0004873 (2004-01-01), Rickes et al.
patent: 11-339499 (1999-12-01), None
patent: 2000-067599 (2000-03-01), None

Affiliated with

Also associated with

Rating

Parallel compression test circuit of memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Parallel compression test circuit of memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Parallel compression test circuit of memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3726588