Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1999-03-23
2002-08-27
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C365S201000
Reexamination Certificate
active
06442717
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to integrated circuit memory devices and more particularly to circuits and methods for testing memory cell arrays of integrated circuit memory devices.
BACKGROUND OF THE INVENTION
Integrated circuit memory devices are widely used in consumer and commercial electronics. As the integration density of these devices continues to increase, the number of cells in a memory cell array may continue to increase. With the increased number of memory cells, it may become increasingly difficult to test the memory cell array.
As is well known to those of skill in the art, a memory cell array generally includes a plurality of data line outputs. In a normal, non-test mode, the data on the data line outputs is transmitted to global output lines. In contrast, in a parallel bit test mode in which a plurality of data bits are concurrently output for comparison testing, a separate parallel bit test circuit may be used. In a conventional parallel bit test circuit, a plurality of data units controlled by one column select line are output through a sense amplifier. The output data is selected in groups of two to be compared in a primary comparison. The compared data in the primary comparison is again selected in groups of two to be compared in a secondary comparison, and the compared data in the secondary comparison are again selected in groups of two to be compared in a tertiary comparison. Thus, the comparison operation may be extended. Separate output drivers may be provided for each of the compared data units. Signals output by each of the output drivers may be transmitted to an output multiplexer.
Referring now to
FIG. 7
, conventional parallel bit test circuits and methods include normal drivers
701
,
703
,
705
,
707
,
709
,
711
,
713
and
715
. In a memory cell array
760
, eight data units are amplified by corresponding sense amplifiers to become data line outputs TD
00
/TD
0
BO, TD
01
/TD
0
B
1
, TD
02
/TD
0
B
2
, TD
03
/TD
0
B
3
, TD
04
/TD
0
B
4
, TD
05
/TD
0
B
5
, TD
06
/TD
0
B
6
and TD
07
/TD
0
B
7
. The normal drivers
701
,
703
,
705
,
707
,
709
,
711
,
713
and
715
, in a normal output mode, respectively transmit the corresponding data line outputs TD
00
, TD
01
, TD
02
, TD
03
, TD
04
, TD
05
, TD
06
and TD
07
to global output lines FDI
00
, FDI
01
, FDI
02
, FDI
03
, FDI
04
, FDI
05
, FDI
06
and FDI
07
. In the parallel bit test mode, data of the data line outputs TD
00
, TD
01
, TD
02
, TD
03
, TD
04
, TD
0
S, TD
06
and TD
07
is compared in response to a selection signal that indicates a selected number of compared bits and outputs the compared signals. The test drivers
761
,
763
,
765
,
767
,
769
,
771
and
773
receive corresponding output signals of the data comparison.
The parallel bit test circuit includes primary comparators
727
,
729
,
731
and
733
, primary switches
735
,
737
,
739
and
741
, secondary comparators
743
and
745
, secondary switches
747
and
749
, a tertiary comparator
751
and a tertiary switch
759
. The primary comparator
727
compares TD
00
to TD
01
to output the primary compared signal FCOO. The primary comparator
729
compares TD
02
to TD
03
to output the primary compared signal FC
01
. The primary comparator
731
compares TD
04
to TD
05
to output the primary compared signal FC
02
. The primary comparator
733
compares TD
06
to TD
07
to output the primary compared signal FC
03
. Also, in the primary parallel test mode, the primary switch
735
receives FC
00
to output FC
00
to an input terminal of the test driver
761
. In the primary parallel test mode, the second switch
737
receives FC
01
to output FC
01
to an input terminal of the test driver
763
. In the primary parallel test mode, the primary switch
739
receives FC
02
to output FC
02
to an input terminal of the test driver
765
. In the primary parallel test mode, the primary switch
741
receives FC
03
to output FC
03
to an input terminal of the test driver
767
.
The secondary comparator
743
compares FC
00
to FC
01
to output a secondary compared signal SC
00
. The secondary comparator
745
compares FC
02
to FC
03
to output a secondary compared signal SC
01
. In the secondary parallel test mode, the secondary switch
747
receives SC
00
to output SC
00
to an input terminal of the test driver
769
. In the secondary parallel test mode, the secondary switch
749
receives SC
01
to output SC
0
L to an input terminal of the test driver
771
.
The tertiary comparator
751
compares SC
00
to SC
0
L to output a tertiary compared signal TC
0
. In the tertiary parallel test mode, the tertiary switch
759
receives TC
0
to output TC
0
to an input terminal of the test driver
773
.
Since the distance between a sense amplifier and a multiplexer may vary based on the internal layout of the integrated circuit, the size of the drivers
761
,
763
,
765
,
767
,
769
,
771
and
773
that drive some of the multiplexers may need to increase. Moreover, the number of output drivers may depend on the number of comparisons.
Accordingly, conventional parallel bit test circuits and methods may consume an excessive area in an integrated circuit memory device. Moreover, since the number and/or size of drivers connected to the data output lines may vary, a difference in speed between input and output data in normal mode may be produced.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved circuits and methods for testing integrated circuit memory devices.
It is another object of the present invention to provide integrated circuit memory device testing circuits and methods that need not unduly increase the integrated circuit area that is occupied by test circuitry.
It is still another object of the present invention to provide integrated circuit memory testing circuits and methods that can reduce the speed differences between input and output data in normal mode.
These and other objects are provided according to the present invention by integrated circuit memory device testing circuits and methods that compare data on a selected number of the data line outputs of a memory cell array to one another to produce comparison results, in response to a selection signal that indicates the selected number of the data line outputs to be compared to one another. A shared test driver is responsive to the comparison circuit to provide the comparison results to an associated global output line for at least two values of the selection signal that indicate at least two selected numbers of data line inputs to be compared to one another. By sharing test drivers, separate test drivers need not be provided for each selected number of the data line outputs that are compared to one another. The number of test drivers may therefore be reduced so that the area occupied by the testing circuits may be reduced.
More specifically, circuits and methods for testing data on data line outputs of a memory cell array includes a plurality of normal drivers that transmit the data on the data line outputs to global output lines in a normal output mode. Comparison circuits and methods compare the data on a selected number of the data line outputs to one another to produce comparison results, in response to a selection signal that indicates the selected number of the data line outputs to be compared to one another, in a parallel bit test mode. The normal drivers preferably do not transmit the data on the data line outputs to the global output lines in the parallel bit test mode.
A plurality of shared test drivers are responsive to the comparison circuit to provide the comparison results to at least one of the global output lines for at least two values of the selection signal. Preferably at least one of the test drivers is responsive to the comparison circuit to provide the comparison results to an associated global output line for at least two values of the selection signal that indicate at least two selected numbers of data line inputs to be compared to one another. Accordingly, the number of
De'cady Albert
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
Torres Joseph D.
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