Parallel bit test circuit in semiconductor memory device and...

Details Parallel bit test circuit in semiconductor memory device and... Parallel bit test circuit in semiconductor memory device and...

2005-06-10

2009-02-24

Abraham, Esaw T (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S735000, C714S789000, C365S201000, C324S210000

Reexamination Certificate

active

07496808

ABSTRACT:
An embodiment is a circuit including 2n−1first comparators to generate a first result by comparing data from at least two of 2nmemory cells to which test pattern data are written. 2n−1first switching circuits provide the first result or a disable signal responsive to a first switching signal. And 2n−2second comparators generate a second result by comparing signals output from some of the 2n−1first switching circuits. N may be a natural number greater than or equal to three.

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English language abstract of the Japanese Publication No. 10-10204.
English language abstract of the Japanese Publication No. 2002-260398.

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