Parallel bit test circuit for testing a semiconductor device in

Details Parallel bit test circuit for testing a semiconductor device in Parallel bit test circuit for testing a semiconductor device in

1997-08-11

1999-11-23

Tu, Trinh L.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

714735, 714819, G11C 2900, G06F 702

Patent

active

059919035

ABSTRACT:
A novel parallel bit test circuit is provided to test a semiconductor memory device which comprises a number of memory cell arrays each having a plurality of memory cells, a word line provided in each memory cell array to commonly connect with the plurality of memory cells, and a plurality of I/O (input/output) lines respectively connected with the plurality of memory cells of each memory cell array. The parallel bit test circuit for testing the plurality of memory cells in parallel bits comprises a comparator for comparing the data of the memory cells with an externally input data to produce a test signal applied to a data I/O terminal.

REFERENCES:
patent: 5164918 (1992-11-01), Ogino et al.
patent: 5400281 (1995-03-01), Morigami
patent: 5483493 (1996-01-01), Shin
patent: 5706234 (1998-01-01), Pilch, Jr. et al.
patent: 5793685 (1998-08-01), Suma

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