Parallel access testing of a memory array

Details Parallel access testing of a memory array Parallel access testing of a memory array

1998-05-28

1999-11-09

Nelms, David

Static information storage and retrieval

Read/write circuit

Testing

G11C 700

Patent

active

059826843

ABSTRACT:
The present invention discloses a method and apparatus for testing a memory array. The memory array includes a plurality of memory blocks. A test data item is written to the memory blocks at a pre-determined location in parallel. The data from the memory blocks are read at the pre-determined location in parallel. These data items are compared to determine if they are identical. One of these data items is compared with the test data item.

REFERENCES:
patent: 4868823 (1989-09-01), White, Jr. et al.
patent: 5471480 (1995-11-01), You
patent: 5673270 (1997-09-01), Tsujimoto
patent: 5910923 (1999-01-01), Brown et al.

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