Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
2001-12-14
2003-05-20
Clark, Jasmine J B (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257S686000, C257S777000
Reexamination Certificate
active
06566746
ABSTRACT:
STATEMENT RE: FEDERALLY SPONSORED RESEARCH/DEVELOPMENT
(Not Applicable)
BACKGROUND OF THE INVENTION
The present invention relates generally to chip stacks, and more particularly to a chip stack having connections routed from the bottom to the perimeter thereof to allow multiple integrated circuit chips such as BGA devices to be quickly, easily and inexpensively vertically interconnected in a volumetrically efficient manner.
Multiple techniques are currently employed in the prior art to increase memory capacity on a printed circuit board. Such techniques include the use of larger memory chips, if available, and increasing the size of the circuit board for purposes of allowing the same to accommodate more memory devices or chips. In another technique, vertical plug-in boards are used to increase the height of the circuit board to allow the same to accommodate additional memory devices or chips.
Perhaps one of the most commonly used techniques to increase memory capacity is the stacking of memory devices into a vertical chip stack, sometimes referred to as 3D packaging or Z-Stacking. In the Z-Stacking process, from two (2) to as many as eight (8) memory devices or other integrated circuit (IC) chips are interconnected in a single component (i.e., chip stack) which is mountable to the “footprint” typically used for a single package device such as a packaged chip. The Z-Stacking process has been found to be volumetrically efficient, with packaged chips in TSOP (thin small outline package) or LCC (leadless chip carrier) form generally being considered to be the easiest to use in relation thereto. Though bare dies or chips may also be used in the Z-Stacking process, such use tends to make the stacking process more complex and not well suited to automation.
In the Z-Stacking process, the IC chips or packaged chips must, in addition to being formed into a stack, be electrically interconnected to each other in a desired manner. There is known in the prior art various different arrangements and techniques for electrically interconnecting the IC chips or packaged chips within a stack. Examples of such arrangements and techniques are disclosed in Applicant's U.S. Pat. No. 4,956,694 entitled INTEGRATED CIRCUIT CHIP STACKING issued Sep. 11, 1990, U.S. Pat. No. 5,612,570 entitled CHIP STACK AND METHOD OF MAKING SAME issued Mar. 18, 1997, and U.S. Pat. No. 5,869,353 entitled MODULAR PANEL STACKING PROCESS issued Feb. 9, 1999.
The various arrangements and techniques described in these issued patents and other currently pending patent applications of Applicant have been found to provide chip stacks which are relatively easy and inexpensive to manufacture, and are well suited for use in a multitude of differing applications. The present invention provides yet a further alternative arrangement and technique for forming a volumetrically efficient chip stack. In the chip stack of the present invention, connections are routed from the bottom of the chip stack to the perimeter thereof so that interconnections can be made vertically which allows multiple integrated circuit chips such as BGA, CSP, fine pitch BGA, or flip chip devices to be stacked in a manner providing the potential for significant increases in the production rate of the chip stack and resultant reductions in the cost thereof.
BRIEF SUMMARY OF THE INVENTION
In accordance with the present invention, there is provided a chip stack comprising a base layer which includes a base substrate having a first conductive pattern disposed thereon. The chip stack further comprises at least one interconnect frame having a second conductive pattern disposed thereon which is electrically connected to the first conductive pattern of the base layer. Also included in the chip stack is a transposer layer which itself comprises a transposer substrate having a third conductive pattern disposed thereon. The third conductive pattern of the transposer substrate is electrically connected to the second conductive pattern of the interconnect frame. In addition to the base and transposer layers and interconnect frame, the chip stack comprises at least two integrated circuit chip packages which are electrically connected to respective ones of the first and third conductive patterns. The interconnect frame is disposed between the base and transposer layers, with one of the integrated circuit chip packages being at least partially circumvented by the interconnect frame. The integrated circuit chip packages may each comprise a CSP device, with the third conductive pattern of the transposer layer being uniquely sized and configured to provide a TSOP interface for the chip stack.
Further in accordance with the present invention, there is provided a chip stack comprising a base layer which includes a base substrate having a first conductive pattern disposed thereon. In addition to the base layer, the chip stack comprises at least one interconnect frame having a second conductive pattern disposed thereon which is electrically connected to the first conductive pattern of the base layer and electrically connectable to another component. In addition to the base layer and interconnect frame, the chip stack comprises at least two integrated circuit chip packages. One of the integrated circuit chip packages is electrically connected to the first conductive pattern of the base layer, with the remaining one of the integrated circuit chip packages being attached (as opposed to electrically connected) to an opposed side of the base substrate and at least partially circumvented by the interconnect frame. Each of the integrated circuit chip packages includes a plurality of conductive contacts, with the second conductive pattern of the interconnect frame and the conductive contacts of the integrated circuit chip package circumvented thereby collectively defining a composite footprint of the chip stack which is electrically connectable to another component.
Still further in accordance with the present invention, there is provided a chip stack comprising a base layer including a base substrate having a first conductive pattern disposed thereon. The chip stack further comprises at least one interconnect frame having a second conductive pattern disposed thereon which is electrically connected to the first conductive pattern of the base layer and electrically connectable to another component. Also included in the chip stack are at least two integrated circuit chip packages which are each electrically connected to the first conductive pattern and disposed on opposed sides of the base substrate. One of the integrated circuit chip packages is at least partially circumvented by the interconnect frame.
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Isaak Harlan R.
Roeters Glen E.
Ross Andrew C.
Clark Jasmine J B
DPAC Technologies Corp.
Stetina Brunda Garred & Brucker
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