Page mode mask ROM using a two-stage latch circuit and a method

Details Page mode mask ROM using a two-stage latch circuit and a method Page mode mask ROM using a two-stage latch circuit and a method

1996-06-07

1997-11-25

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

3652335, 3652385, G11C 700

Patent

active

056919433

ABSTRACT:
The present invention discloses provides a page mode mask ROM capable of decreasing sense amplifiers by latching data using a two-stage latch circuit. Accordingly, the present invention provides a method for decreasing the number of amplifiers in memory device including an Y-predecoder, an Y-decoder, amplifiers and a cell array, said method comprising of the steps of: generating clock signals according to an address transition pulse; generating enable signal for driving said Y-predecoder and said amplifiers in response to said clock signals and said address transition pulse; amplifying data stored in said cell array in response to the output from said Y-decoder; latching the amplified data in a latch means; and transferring the latched data in said latch means to another latch means under the control of an address transition pulse generated whenever address transition occurs.

REFERENCES:
patent: 5295117 (1994-03-01), Okada
patent: 5305284 (1994-04-01), Iwase

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