Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2009-04-07
2010-02-23
Nguyen, Viet Q (Department: 2827)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S189011, C365S189140, C365S189170, C365S189080, C365S185220
Reexamination Certificate
active
07668023
ABSTRACT:
A page buffer circuit of a memory device including a plurality of Multi-Level Cells (MLCs) connected to at least a pair of bit lines includes a Most Significant Bit (MSB) latch, a Least Significant Bit (LSB) latch, a data I/O circuit, an inverted output circuit, a MSB verification circuit, and a LSB verification circuit. The MSB latch is configured to sense a voltage of a sensing node in response to a control signal and store an upper sensing data, and output an inverted upper sensing data, or store an input data and output an inverted input data. The LSB latch is configured to sense a voltage of the sensing node in response to the control signal, and store and output a lower sensing data, or store and output an input data received through the MSB latch. The data I/O circuit is connected to the MSB latch and a data I/O line, and is configured to perform the input and output of a sensing data or the input and output of a program data.
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Hynix / Semiconductor Inc.
Nguyen Viet Q
Townsend and Townsend / and Crew LLP
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