Page buffer circuit, nonvolatile memory device including the...

Details Page buffer circuit, nonvolatile memory device including the... Page buffer circuit, nonvolatile memory device including the...

2011-03-01

2011-03-01

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S230080

Reexamination Certificate

active

07898876

ABSTRACT:
A page buffer circuit comprises a bit line selection unit, a latch unit, and a bit line control unit. The bit line selection unit is configured to select a bit line coupled to memory cells. The latch unit comprises a plurality of latch circuits. The plurality of latch circuits is coupled to a sense node and configured to latch data to be programmed into the memory cells or store data from the memory cells. The bit line control unit is coupled to the sense node and configured to temporarily charge a voltage of the selected bit line in response to charge and transfer control signals or transfer the charged voltage to the selected bit line.

REFERENCES:
patent: 7298648 (2007-11-01), Lee et al.
patent: 10-0244864 (2000-03-01), None
Notice of Preliminary Rejection issued from Korean Intellectual Property Office on Jun. 28, 2010.

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